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Hello Johnny, Nice to meet you. Thank you for your good question! In a digital DSP architecture, the 8 taps and 9 FFE taps in the digital FIR part are typically used to improve the signal integrity and compensate for channel distortions and reflection. The number of taps corresponds to the amount of filtering or equalization applied to the signal to counteract effects such as inter-symbol interference (ISI) caused by the channel and other discontinuity. Regarding your second question, the FFE in the digital DSP architecture is similar in concept to the FFE in analog architectures, but they differ in implementation. While the analog FFE typically involves adjusting the amplitude of the input signal at different time intervals, the digital FFE in a DSP architecture works by applying digital taps to the sampled signal, allowing for finer control and more complex equalization. The reason for having so many taps in the digital architecture is to provide a more accurate equalization process, especially in high-speed communication systems, where more taps can help mitigate significant channel impairments. As for the 802.ck and OIF-CEI specifications specifying up to 5 taps, those guidelines generally refer to the minimum requirements for certain designs, and manufacturers often go beyond those to optimize the system for better performance. I hope this helps clarify the issue! Let me know if you have further questions. Best regards, CC

@@circuitimage Thank you very much for your patient and detailed explanation; it has been very helpful to me. I have noticed that the analog FFE architecture transmitter is more commonly used in the VSR and XSR domains, likely to achieve lower power consumption for transmitters operating in channels with less loss. From my understanding, when the required number of FFE taps increases, the 2-step coarse-fine architecture struggles to achieve more than 5 taps using the C4 clock. (IBM's 24' VLSI introduced tap extension modules but could only achieve 5 FFE taps, while UCB's 22' JSSC approach seems to allow for more taps but with higher power consumption.) Additionally, the limited number of segmented driver slices also restricts the number of analog FFE taps. On the other hand, using SST-driver voltage-mode FFE architecture for multiple taps requires too many DRV slices. Alternatively, employing an LUT-based analog FFE transmitter for more taps significantly impacts the size of the LUT module and increases power consumption. In contrast, achieving multiple taps in a digital DSP architecture is relatively straightforward, with precision mainly dependent on the bit width of the serialized DAC slices. The digital DSP only needs to convert the desired voltage levels into control words to manipulate the DAC slices. If I have misunderstood anything, I would appreciate your guidance. Thank you once again for your response, Dr. Chen.

Hi ZZZ, Nice to meet you, and thank you for the good question. You are correct. With very high channel loss (e.g., 30dB), the signal's eye diagram can become closed, especially if the number of DFE taps is not large enough. In such cases, using only the DFE mode to equalize the 30dB loss would not be power efficient. Thanks, CC

@ Nice to meet you too. And thank you for your reply. However, what I mean is that if the data itself cannot correctly distinguish between 1 and 0 under high channel loss, wouldn't this mean that even with a DFE with many taps, it still cannot be used because the decision is already incorrect which would cause error propagation.

Hi E A, thank you for bringing up the mic issue. I'll make sure to get a better mic to address the problem you mentioned. 🙏

Hi 젊은꼰대, Thank you for your message and kind words! I’d be happy to assist. Once I have the script ready, I’ll take it and let you know.

Hi Hrachya, It’s great to meet you! Thank you🙏 for your kind words about the video-I’m glad you found it helpful. I’m doing well, and I hope you are too. 😊 You’ve raised an excellent question about the speed of the CMFB loop and its role in addressing variations in the common mode. Let me clarify a few points: Tracking Power Supply Noise You’re absolutely right that variations in the power supply can cause common-mode drift, especially due to their impact on devices like M3 and M4 (as you mentioned at 7:11). The CMFB loop is designed to mitigate these variations by adjusting the current to stabilize the common mode around VREF. Designing the CMFB for These Variations To effectively track and correct these variations, the CMFB loop needs sufficient bandwidth to respond to the expected noise frequencies. However, this involves trade-offs: Resistor Sizes: Smaller resistors in the CMFB sensing network can reduce RC time constants, improving the loop’s response speed. However, this may reduce the gain and compromise the accuracy of the common-mode voltage. Bandwidth of the Gm Amplifier: A wider bandwidth for the Gm amplifier enables faster response to variations but requires careful design to avoid instability. Additionally, increasing the bandwidth can lead to higher power consumption, which is critical to manage since the CMFB loop shouldn’t consume more power than the main amplification path. Practical Design Approach The CMFB loop’s bandwidth should ideally be sufficient to address the dominant frequency components of expected variations (e.g., supply noise frequencies). At the same time, it’s important to ensure that the CMFB loop doesn’t interfere with other operational aspects of the circuit, such as the main signal path. Let me know if you have any further questions or would like to discuss this in more detail. It’s always great to dive into these design considerations! 😊 Best regards, CC

​@@circuitimage Thank you for the detailed response. I really appreciate that ! 😊

Hi 育瑛, yes, thank you for the good suggestion. I'll put it in my to-do lists. :)

@@circuitimage Thanks a lot

Hi Improooover, Thanks for the feedback-I’m glad that helped. I’m working on adding more diverse content on wireline systems to ensure that everyone, or more people, can benefit from it. Best regards, CC

Hi Enson, thanks for your good question. You're correct: the sampler's decision is made by the input differential inputs, not the single-ended signal. I might have caused the confusion in my video. Could you please point me out where I made the confusion in my video? Thanks again for your feedback. CC

​@@circuitimagethanks for the reply In 2:50 I was wondering if the differential signal is connected to the sampler than why DC offset will reduce the decision margin

​@@ensonb9328Hi Enson, thanks for pointing it out clearly. You're correct. It's the differential signal, so the decision margin would be the swing related to the 0V. But, if the offset of the differential signal would make the differential decision threshold not 0V anymore. Instead, the differential decision threshold would be the VOS, and the DC offset ,VOS, will reduce the differential decision margin with the same differential swing. Thanks again for your feedback. I hope it's more clear to you now. :) CC

@@ensonb9328 Hi Enson, Apologies for the delayed response. I thought I had replied but realized it didn’t go through properly. To clarify, the differential signal is connected to the sampler, with the ground (0V) serving as the reference for the corresponding differential signal. However, the DC offset shifts the reference decision point to be either above or below 0V. When the differential signal falls above this adjusted reference, the decision margin decreases accordingly. Does that make sense? Thanks, CC

Hi Zatoichi, Nice to meet you and I'm sorry for my poor accent and the inconvenience. I've put in the subtitles as much as I can. Could you please turn it on as a workaround? I hope that helps. :) Thanks, CC

@ Your material is very good and I’d really like to learn what you can teach us. Thank you!

​@@ZatoichiRCS Hi Zatoichi, Thanks for the additional feedback. I'm glad that helps. I'm happy to help. Thanks, CC

Hi Lab_mangeSQE, thanks for the feedback. I'm glad that helps your understanding. :)

Hi 목정수, Nice to meet you. Thank you so much for the good question. That's a low-pass effect along with the settling behavior. Lower frequencies propagate more effectively than higher frequencies and cause h1 (post cursor) larger than h-1 (precursor). If that's not clear to you, I can make another video to explain it w/ more images. :) Thanks, CC

@@circuitimage Thank you for your answer. I appreciate it if you do. I will try to understand the answer. I have been greatly helped in studying CDR and DFE through your videos. Thanks for the great videos.

@@목정수-z3y Hi 목정수, thanks for your feedback 🙏and I'm glad those videos help, which motives me to do more. 😉

Hi Gagandeep, Nice to meet you. Are you asking basics in an ADC? If that's the case, you can read "Analog-to-Digital Conversion" by Marcel Pelgrom. Thanks, CC

Hi Starry, you're very welcome. 😊🙏

Hi Angelia, Thanks for the good questions. 🙏 I have other videos talking about how much shift up/dn/left/right should be evaluated, respectively, such that you'll know the good margin for your specific design. 1. how much shift up/dn? Why Link Budget in A SerDes (1)-Eye Height? ruclips.net/video/CpCkVHohNGc/видео.htmlsi=2ZaHIEVdzG_7gwM2 2. how much shift left/right? Why Link Budget in A SerDes (2) - Eye Width? ruclips.net/video/YxvvZ2MfiCQ/видео.htmlsi=2VFd2Q5BlG5J1AlA Thanks, CC

@@circuitimage Hi CC, thanks much for the Eye Height & Eye Width vedio. I wondered the up/down with 35mV and 7 or 8%UI left/right shift in this 2D vedio. But after watchig this 2D vedio again, I think I get what you mean about the interaction on "page 15", thanks a lot~~ 😄

Hi Angelia, thanks for the feedback 🙏 and I'm glad my videos help. 😊 You're correct. 😉 I graduated from NTU GIEE from Prof Tsao & Prof. Wang group. :)

Hi Aadhya’s, Nice to meet you. Thanks for the good questions. No. MM CDR does not require the transition, but its performance will highly depend on the channel & EQ frequency response. So, the bang-bang CDR is more robust at a higher channel loss. Thanks, CC

Hi Bobby, That's a good question. 😊 It is, but I think the area overhead is not that many. I can try to analyze it to provide a few ballpark numbers for you in other videos. Thanks, CC

@@circuitimage Thanks CC. Look forward to the new videos.

@@bobbylu3490 Sure. My pleasure. :)

Hi Lianhua, nice to meet you and thank you so much for the good suggestions. I'll do that and inform you later. :)

Hi ToS, you're very welcome. :)

Glad you enjoyed it 🥰

Hi OSeyedian, nice to meet you. Thanks you so much for your feedback and I'm glad information was valuable to you. :)

Hi Green tangle, nice to meet you and thanks for the suggestions. I'll do the ADPLL. But I had a few VCOs here: 1. LC VCO Multiphase: ruclips.net/video/J0bKPaAbvxU/видео.html 2. Feed-forward Delay Cell for A Ring-based VCO: ruclips.net/video/kqL3HRjlums/видео.html 3. Multiphase VCO for An NRZ or PAM4: ruclips.net/video/lnj6xSTLuOI/видео.html Please let me know what else you need

Hi Lab_mangement, thanks for the feedback and I'm glad that you liked it. :)

Hi Greywhittef, Thanks for the good suggestions and I'll do it. :) Thanks, CC

Hi Joseph, Thanks for the good questions. I have comments below. What are the practical pros and cons of impulse response simulation vs numerically calculating the difference between two step response (a positive and negative step response) simulations? [CC] Are you asking about the correlation between the single-shot align with the two step responses? If yes, my understanding is that it should be equivalent if both responses don't saturate the system, which only assumes the passive elements of the lossy channel. :) Thanks, CC

Hi SUMAN, Thanks for the good questions. I have comments below. Thanks for the video. I have a question. The minimum amount of Swing at the Slicer input is decided by "BER/Slicer input noise/Sensitivity/offset" ? What limits the max side? Can we have very High Swing at the Slicer input for both High and low frequency components of the signal? [CC] The maximum swing may distort the linearity of the summing amplifier and then the DFE might not work well. In addition, there's a reliability issue if the maximum swing was not considered in the design. @1:40 : You tell for less dynamic range , sampling accuracy be increased or clockJitter power requirement is reduced? Can you explain in some more detail? [CC] The less dynamic range may help mitigate the sampler's hysteresis and perform faster with a less clock to Q or input setup time. Then the clock requirements of the sampler can be reduced. Thanks, CC

Hi 育瑛,Thanks for the feedback.🙏 Your understanding for the whole PLL loop operation is correct. 😊

@@circuitimage Thanks for the prompt reply!!

Hi Lab_mangement, thanks for your feedback. Yes, the eys is is very important for measuring super high Speed data analysis. :)

👍👍😔​@@circuitimage

Hi Christiane, thanks for feedback.

Hi Patricia, thanks for the feedback. :)

Hi Melissa, nice to meet you and thank you for feedback. :)

Hi Eric, nice to meet you. :)

Hi Kobe, thanks for the good question. The big DAC could have lots of parasitic on the high speed routing.

@@circuitimage CC,thanks for your reply,

@@KobeJames-ii4lz You're very welcome. :) Have a nice weekend!!

Hi @arnaud.lancelot, thanks for the feedback. Could you please elaborate on your concern?

@@circuitimage If the diff pair acts like an integrator, the gain has the form of gm/C. The input noise is (kt/C) /(gain x gain) . So input noise should look like kTxC/(gm x gm). So boost the gm transconductance for sure but diminish the capacitance C.

@@arnaud.lancelot I agree. So, in my video, I mentioned, the bigger C the less noise, but the speed goes down.

@@circuitimage What i m saying is that you should look at the SNR, signal to noise ratio. The smaller the capacitance, the lower the noise from... the input perspective. So you increase the SNR at the input. But you also increase it at the output (gmxgmxVxV/CxC)/(kT/C) ~1/C So you reduce C. you go faster and has a better SNR. Reducing the noise is useless if you reduce even more the signal gain.

@@arnaud.lancelot Thanks for the feedback, 🙏 and I agree with your SNR, which should match the input referred noise, which is the ouptut noise/gain, not just noise itself. 🎉😊

Hi Ahmad, Nice to meet you and thank you 🙏 for your questions. Since the channel frequency response was not equal loss over frequency, so we need to equalize it. 😊

@@circuitimage channel frequency response loss didn't equal the which frequency?

@@NostalgiaT Ideally, you want the gain is the same over your interested frequency, which is flat. But a lossy channel isn't flat.

@@NostalgiaT This CTLE ruclips.net/video/zsuJMqadaKY/видео.htmlsi=vpxIC-vZPHHTYV3d may show it.

Hi Ahmad, Nice to meet you and thank you 🙏 for your questions. Lots difference and you might want to check all my videos😊

Thank you!!

Hi Hanyue, Nice to meet you. Thanks for the good suggestion. Yes, that's correct. The 3D packaging helps the implementations of the Chiplet. Thanks, CC

Hi Shivangi, Nice to meet you. Thanks for the good feedback. The 5GHz would be the Nyquist rate of 10Gbps. Thanks, CC

​@@circuitimage Thanks for your response... But it would be quite helpful if you can explain this..I am a bit confused

​@@betu1207 Hi Shivangi, Sure. The simplest way of thinking about this is taking the maximum transition from any data pattern is the clock pattern, which is 1010. For example, the 1UI of the 10Gbps is 100ps, but the 1010 or clock pattern is 5GHz since the clock period is 200ps instead of 100ps or 50ps, so 5GHz is the Nyquist rate of the 10Gbps.

Hi Kobe, sure. Nice to meet you. :) Is this ( ruclips.net/video/YsFg_ReBBzQ/видео.html ) you're looking for?

Hi Abhirup, Thank you 🙏 so much for your feedback, which I agree with a lot. My PCI-Gen5 32Gbps also applied PLL's 16GHz clock.😊 I'll put your comments in my next video: "Why half-rate or quarter-rate DFE." 😊

@@circuitimage great, look forward CC.

@@abhiruplahiri1 Thanks for your always support. :)

Hi 장구, Nice to meet you. Thank you 🙏 so much for your feedback, which I agree with a lot. I'll put your comments in my next video: "Why half-rate or quarter-rate DFE." 😊

Hi Matthew, Nice to meet you. Thank you 🙏 so much for your corrections and for looking carefully, accidentally adding extra "the of".

Hi Pran, nice to meet you and thank you for the suggestions. Is this (ruclips.net/video/BZLVH-8JFys/видео.htmlsi=vhs3nMSafdXXshHz) you're looking for?

Hi Yifeng, thanks for the question. Could you please elaborate on which time your refer to?