Hello teacher, I have a question to ask you. Why does the transmitter of digital DSP architecture need to make 8 taps and 9 FFE of tap in the digital Fir part? Is the FFE here the same as the FFE of the analog FFE transmitter architecture? If so, why do you need to do so many? I see that the number of tap specified by the 802.ck and OIF-CEI is up to 5. I hope you can answer it. It's been bothering me for a long time.
Hello Johnny, Nice to meet you. Thank you for your good question! In a digital DSP architecture, the 8 taps and 9 FFE taps in the digital FIR part are typically used to improve the signal integrity and compensate for channel distortions and reflection. The number of taps corresponds to the amount of filtering or equalization applied to the signal to counteract effects such as inter-symbol interference (ISI) caused by the channel and other discontinuity. Regarding your second question, the FFE in the digital DSP architecture is similar in concept to the FFE in analog architectures, but they differ in implementation. While the analog FFE typically involves adjusting the amplitude of the input signal at different time intervals, the digital FFE in a DSP architecture works by applying digital taps to the sampled signal, allowing for finer control and more complex equalization. The reason for having so many taps in the digital architecture is to provide a more accurate equalization process, especially in high-speed communication systems, where more taps can help mitigate significant channel impairments. As for the 802.ck and OIF-CEI specifications specifying up to 5 taps, those guidelines generally refer to the minimum requirements for certain designs, and manufacturers often go beyond those to optimize the system for better performance. I hope this helps clarify the issue! Let me know if you have further questions. Best regards, CC
@@circuitimage Thank you very much for your patient and detailed explanation; it has been very helpful to me. I have noticed that the analog FFE architecture transmitter is more commonly used in the VSR and XSR domains, likely to achieve lower power consumption for transmitters operating in channels with less loss. From my understanding, when the required number of FFE taps increases, the 2-step coarse-fine architecture struggles to achieve more than 5 taps using the C4 clock. (IBM's 24' VLSI introduced tap extension modules but could only achieve 5 FFE taps, while UCB's 22' JSSC approach seems to allow for more taps but with higher power consumption.) Additionally, the limited number of segmented driver slices also restricts the number of analog FFE taps. On the other hand, using SST-driver voltage-mode FFE architecture for multiple taps requires too many DRV slices. Alternatively, employing an LUT-based analog FFE transmitter for more taps significantly impacts the size of the LUT module and increases power consumption. In contrast, achieving multiple taps in a digital DSP architecture is relatively straightforward, with precision mainly dependent on the bit width of the serialized DAC slices. The digital DSP only needs to convert the desired voltage levels into control words to manipulate the DAC slices. If I have misunderstood anything, I would appreciate your guidance. Thank you once again for your response, Dr. Chen.
Hello teacher, I have a question to ask you. Why does the transmitter of digital DSP architecture need to make 8 taps and 9 FFE of tap in the digital Fir part? Is the FFE here the same as the FFE of the analog FFE transmitter architecture? If so, why do you need to do so many? I see that the number of tap specified by the 802.ck and OIF-CEI is up to 5. I hope you can answer it. It's been bothering me for a long time.
Hello Johnny,
Nice to meet you. Thank you for your good question!
In a digital DSP architecture, the 8 taps and 9 FFE taps in the digital FIR part are typically used to improve the signal integrity and compensate for channel distortions and reflection. The number of taps corresponds to the amount of filtering or equalization applied to the signal to counteract effects such as inter-symbol interference (ISI) caused by the channel and other discontinuity.
Regarding your second question, the FFE in the digital DSP architecture is similar in concept to the FFE in analog architectures, but they differ in implementation. While the analog FFE typically involves adjusting the amplitude of the input signal at different time intervals, the digital FFE in a DSP architecture works by applying digital taps to the sampled signal, allowing for finer control and more complex equalization. The reason for having so many taps in the digital architecture is to provide a more accurate equalization process, especially in high-speed communication systems, where more taps can help mitigate significant channel impairments.
As for the 802.ck and OIF-CEI specifications specifying up to 5 taps, those guidelines generally refer to the minimum requirements for certain designs, and manufacturers often go beyond those to optimize the system for better performance.
I hope this helps clarify the issue! Let me know if you have further questions.
Best regards,
CC
@@circuitimage Thank you very much for your patient and detailed explanation; it has been very helpful to me. I have noticed that the analog FFE architecture transmitter is more commonly used in the VSR and XSR domains, likely to achieve lower power consumption for transmitters operating in channels with less loss. From my understanding, when the required number of FFE taps increases, the 2-step coarse-fine architecture struggles to achieve more than 5 taps using the C4 clock. (IBM's 24' VLSI introduced tap extension modules but could only achieve 5 FFE taps, while UCB's 22' JSSC approach seems to allow for more taps but with higher power consumption.) Additionally, the limited number of segmented driver slices also restricts the number of analog FFE taps. On the other hand, using SST-driver voltage-mode FFE architecture for multiple taps requires too many DRV slices. Alternatively, employing an LUT-based analog FFE transmitter for more taps significantly impacts the size of the LUT module and increases power consumption.
In contrast, achieving multiple taps in a digital DSP architecture is relatively straightforward, with precision mainly dependent on the bit width of the serialized DAC slices. The digital DSP only needs to convert the desired voltage levels into control words to manipulate the DAC slices.
If I have misunderstood anything, I would appreciate your guidance. Thank you once again for your response, Dr. Chen.