Hello ! Great video, I think I have seen the floating tap idea somewhere, probably in 40Gbps serial link. Now I understand concept better. Few questions related to summer. At slide 5, you show the summer implementation. I think the idea is that vin (from CTLE) has the ISI on it, and to remove the ISI from the summer's output (vout), the right side of the circuit sucks part of the Id1 and Id2 currents and corrects the differential voltage on resistors Rd1 and Rd2. So, first question is what are H2[4:0] and H2[5] (I guess these are control bits and somehow related to H2 feedback coefficient). Second question is: it seems that M1 and M2 transistors are controlled by Vin+ and Vin- , which are analog signals with proper common mode. Instead M3, M4, M5, M6 are just switches controlled by D2 (which is either 1 or 0). I am worried that depending on what is the common mode on Vin , the summer might function differently. Or maybe I am wrong? And last question: what is vTH on the leftmost transistor and how M12 is controlled, is it a switch ? Thank you again for your work :)
Hi Hrachya, Thank you so much for the feedback and I'm glad the floating tap idea helped you. I have comments below. Few questions related to summer. At slide 5, you show the summer implementation. I think the idea is that vin (from CTLE) has the ISI on it, and to remove the ISI from the summer's output (vout), the right side of the circuit sucks part of the Id1 and Id2 currents and corrects the differential voltage on resistors Rd1 and Rd2. [CC] YesSo, first question is what are H2[4:0] and H2[5] (I guess these are control bits and somehow related to H2 feedback coefficient).[CC] Yes. H2[5] was the MSB of the tap2 feedback coefficient in sign bits & H2[4:0] was the control bits of the tap2 feedback coefficient in magnitude bits. Second question is: it seems that M1 and M2 transistors are controlled by Vin+ and Vin- , which are analog signals with proper common mode. Instead M3, M4, M5, M6 are just switches controlled by D2 (which is either 1 or 0). I am worried that depending on what is the common mode on Vin, the summer might function differently. Or maybe I am wrong? [CC] Yes. That could operate differently; therefore, adding a CMOS to the CML conversion stage would mitigate the concern you had, but the extra delay stage would violate the close timing. In the real case, people will leave with it but make M3 to M6 devices w/ higher Vth devices while the M1-2 could be ultra-low Vth devices to reduce the different settling behaviors.And last question: what is vTH on the leftmost transistor and how M12 is controlled, is it a switch ? [CC] Yes. You're correct that the M12 is just a switch to control or flexibly tune the tail current. Thank you again for your work :) [CC] You're very welcome.
Hello. I love the way of teaching. Its organized in why and why not a particluar circuit. Intuitive explanation is great to summarize these circuits. I hope this channel receives lots of views. Appreciate your work! Is it possible to get access to the slides?
Thanks for the feedback. There are lots of literature/paper references to the split summers. One of my favorites is this one: "A 1.0625 ∼ 14.025 Gb_s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS." Please let me know if you need anything else from me.
@Nick Liao Thanks for the good question. Yes, that's workable and a realistic design approach. The subtlety is the manufacture QA or variability of the package, which can be good enough nowaday.
Hi Teacher, Thank you for the Great Video. I have heard that if a receiver rely heavily on DFE tap1, it may choose to request Precoding during link training. Do you know why it is? Do you have a video to explain the relationship between DFE and precoding? Thanks!
Hi ZanZ9898, nice to meet you, and thanks for the nice questions. I don't have the video, but could you please elaborate on which or what kind of precoding you referred to, which may help a better understanding of the reason behind it? 😀
@@ZanZ-qi6wz Hi Zan, Thank you so much for the clarification. I understand your concern, which was described in my previous video "Why Adaptation in Discrete-time Equalizers?" (ruclips.net/video/MIPTOMemF_Q/видео.html). You can refer to it and let me know if the image is still not clear to you. :)
Hi CC, Thanks for your great video. At 12:40, what does 7 floating taps mean? Physical connection is tap 1 to 5. From my point of view, 6~14 are floating taps, but the number is 9.
@陳冠宇 Thanks for the good catch and careful watching. My 7 floating taps were referring to the pulse response ~9:29, which shows the 7 floating taps could cancel the post-cursors #10, 11, 12, 29, 30, 31, 32 (7 taps). Other post-cursors are ~0 and the other 2 floating taps might not be needed since the coefficient would be ~0.
Hi CC, If the ISI take place between post -cursor 1 and post-cursor 2 UI, so this ISI cannot be canceled or compensated out, what is the solution for this case?
@Nick Chiang Thanks for the very good question. If that's the residual is small, that's okay. But, if the residual is big, that means the DFE's feedback settling is not fast enough even though the timing was met; therefore, further reducing the DFE close loop delay is a must. Another one is to add the edge-DFE (I can talk about that later), which may add complexity and loading but is very effective.
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Hello ! Great video, I think I have seen the floating tap idea somewhere, probably in 40Gbps serial link. Now I understand concept better.
Few questions related to summer. At slide 5, you show the summer implementation. I think the idea is that vin (from CTLE) has the ISI on it, and to remove the ISI from the summer's output (vout), the right side of the circuit sucks part of the Id1 and Id2 currents and corrects the differential voltage on resistors Rd1 and Rd2.
So, first question is what are H2[4:0] and H2[5] (I guess these are control bits and somehow related to H2 feedback coefficient). Second question is: it seems that M1 and M2 transistors are controlled by Vin+ and Vin- , which are analog signals with proper common mode. Instead M3, M4, M5, M6 are just switches controlled by D2 (which is either 1 or 0). I am worried that depending on what is the common mode on Vin , the summer might function differently. Or maybe I am wrong?
And last question: what is vTH on the leftmost transistor and how M12 is controlled, is it a switch ?
Thank you again for your work :)
Hi Hrachya,
Thank you so much for the feedback and I'm glad the floating tap idea helped you. I have comments below.
Few questions related to summer. At slide 5, you show the summer implementation. I think the idea is that vin (from CTLE) has the ISI on it, and to remove the ISI from the summer's output (vout), the right side of the circuit sucks part of the Id1 and Id2 currents and corrects the differential voltage on resistors Rd1 and Rd2. [CC] YesSo, first question is what are H2[4:0] and H2[5] (I guess these are control bits and somehow related to H2 feedback coefficient).[CC] Yes. H2[5] was the MSB of the tap2 feedback coefficient in sign bits & H2[4:0] was the control bits of the tap2 feedback coefficient in magnitude bits.
Second question is: it seems that M1 and M2 transistors are controlled by Vin+ and Vin- , which are analog signals with proper common mode. Instead M3, M4, M5, M6 are just switches controlled by D2 (which is either 1 or 0). I am worried that depending on what is the common mode on Vin, the summer might function differently. Or maybe I am wrong? [CC] Yes. That could operate differently; therefore, adding a CMOS to the CML conversion stage would mitigate the concern you had, but the extra delay stage would violate the close timing. In the real case, people will leave with it but make M3 to M6 devices w/ higher Vth devices while the M1-2 could be ultra-low Vth devices to reduce the different settling behaviors.And last question: what is vTH on the leftmost transistor and how M12 is controlled, is it a switch ? [CC] Yes. You're correct that the M12 is just a switch to control or flexibly tune the tail current. Thank you again for your work :)
[CC] You're very welcome.
@@circuitimage Thank you for the useful feedback :)
Hello. I love the way of teaching. Its organized in why and why not a particluar circuit. Intuitive explanation is great to summarize these circuits. I hope this channel receives lots of views. Appreciate your work!
Is it possible to get access to the slides?
Hi Kumail, nice to meet you and thank you so much for the feedback. Sorry. I don't have a plan to give access yet. :)
又是乾貨滿滿的一集!
@李茂誠 , 我很高興它有所幫助 :)
Nice video as always. Could you share the literature/paper reference for split summer for the exact circuit, looks interesting? Many thanks.
Thanks for the feedback. There are lots of literature/paper references to the split summers. One of my favorites is this one: "A 1.0625 ∼ 14.025 Gb_s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS." Please let me know if you need anything else from me.
@@circuitimage really appreciate your fast response. Thanks a lot for the input and sharing the paper information. Cheers.
You are very welcome 😄
Hi CC
Thanks for the great video
Is it possible to predict that the chip's DFE taps is suitable for motherboard's connector placement and numbers?
@Nick Liao Thanks for the good question. Yes, that's workable and a realistic design approach. The subtlety is the manufacture QA or variability of the package, which can be good enough nowaday.
Hi Teacher, Thank you for the Great Video. I have heard that if a receiver rely heavily on DFE tap1, it may choose to request Precoding during link training. Do you know why it is? Do you have a video to explain the relationship between DFE and precoding? Thanks!
Hi ZanZ9898, nice to meet you, and thanks for the nice questions. I don't have the video, but could you please elaborate on which or what kind of precoding you referred to, which may help a better understanding of the reason behind it? 😀
@@circuitimage I mean specifically for PCIE Gen5 precoding.
@@ZanZ-qi6wz Hi Zan, Thank you so much for the clarification. I understand your concern, which was described in my previous video "Why Adaptation in Discrete-time Equalizers?" (ruclips.net/video/MIPTOMemF_Q/видео.html). You can refer to it and let me know if the image is still not clear to you. :)
@@circuitimage Thank you again!
@@ZanZ-qi6wz You're very welcome. :)
Hi CC,
Thanks for your great video.
At 12:40, what does 7 floating taps mean?
Physical connection is tap 1 to 5. From my point of view, 6~14 are floating taps, but the number is 9.
@陳冠宇 Thanks for the good catch and careful watching. My 7 floating taps were referring to the pulse response ~9:29, which shows the 7 floating taps could cancel the post-cursors #10, 11, 12, 29, 30, 31, 32 (7 taps). Other post-cursors are ~0 and the other 2 floating taps might not be needed since the coefficient would be ~0.
@@circuitimage Thanks for your clear explanation.
@@hitboy061 I'm glad that helps :)
Hi CC, If the ISI take place between post -cursor 1 and post-cursor 2 UI, so this ISI cannot be canceled or compensated out, what is the solution for this case?
@Nick Chiang Thanks for the very good question. If that's the residual is small, that's okay. But, if the residual is big, that means the DFE's feedback settling is not fast enough even though the timing was met; therefore, further reducing the DFE close loop delay is a must. Another one is to add the edge-DFE (I can talk about that later), which may add complexity and loading but is very effective.
@@circuitimage Thanks! I’m looking forward to seeing the topic of the edge-DFE 😬
@@nickchiang0 Sure. Too many topics people are interested in, so that may take. few times and will give you an update. :)
Hi sir, Can you please make English subtitles properly. Your explanations are very good. But sometimes I fail to understand words you are using
@Debarshee Bhattacharjee Thanks for the suggestions. Done. Could you please check if that's clear to you? Thanks again :)