I am experienced design engineer. This is one of my favorite interview questions related to high speed design - "why not DFE -only"? Just one line but you need to know lot of things to answer that.
Hi, another very useful video :) One question. At 11:21 you provide loop delay formula. I understood that TFB comes for H1 (or H2), TSUM is the summer settling time, TCK_Q is the slicer decision time (looking to first tap, which is the critical one). Basically TCK_Q is determined from the clock edge to the slicer output reaching let's say 90% . However I don't understand what TSetup is, which you mention is sampler's setup time. As far as I know the clock and data are 90 degrees shifted with respect to each other. Is it possible that clock doesn't arrive exactly at 90 degrees shift and this creates additional delay which you denote as TSetup ? Thanks
Hi Hrachya, Thank you for the excellent question. Ideally, w/ the BB or MM CDR, that would be that clock should arrive exactly at 90 degrees. But, if the eye is not symmetric (on average), the BBPD (CDR) would make a shift slightly earlier or later. Similarly or more vulnerable in a MM (Baud-rate) CDR, the pulse response may cause the clock doesn't arrive exactly at 90 degrees shift. I hope those examples can provide insight into those subtleties.
@@circuitimage Thanks a lot for useful info. So, in conclusion the TSetup term in the delay formula is because the clock possibly can arrive not exactly 90 degrees phase shifted ?
Thanks for your video, I have one question about error propagation in DFE, even burst error. For this disadvantage, we usually use THP precoding in PAM-4 mode. But why we seldom use this technique in NRZ mode? Is this related to DFE?
Hi Weili, Nice to meet you and thanks for your excellent questions. You're correct. The PAM-4 has a much less margin (in eye width & eye height) than the NRZ; therefore, the precoding is necessary to mitigate the burst error, which is not very sensitive to NRZ in a DFE usage. You can refer to my other "why PAM4 & NRZ videos" to get more images of both signaling differences. 😉
Hi ZZZ, Nice to meet you, and thank you for the good question. You are correct. With very high channel loss (e.g., 30dB), the signal's eye diagram can become closed, especially if the number of DFE taps is not large enough. In such cases, using only the DFE mode to equalize the 30dB loss would not be power efficient. Thanks, CC
@ Nice to meet you too. And thank you for your reply. However, what I mean is that if the data itself cannot correctly distinguish between 1 and 0 under high channel loss, wouldn't this mean that even with a DFE with many taps, it still cannot be used because the decision is already incorrect which would cause error propagation.
Thanks for the good question. The BER target is very small, e.g., < 1e-12 or 1e-15. Therefore, it's unlikely to be stuck from the error propagation if the DFE works in the beginning with a BER under the target.
I am experienced design engineer. This is one of my favorite interview questions related to high speed design - "why not DFE -only"? Just one line but you need to know lot of things to answer that.
Hi Sai, Thank you so much for your feedback. I agree with your favorite interview questions related to high-speed design - "why not DFE -only" :)
You are doing god's work brother.
Respect from India
Thanks for the feedback and I'm glad to hear it from India.
Great job!
Thanks for taking time and effort to share your knowledge.
Hi Spaceboy,
Nice to meet you. You're very welcome. Thank you for the feedback and I'm glad you liked it. 😀
Hi, Excellent videos. Please post more videos Rx detection, resistor calibration, slicer calibration, CDR loops and IQ calibration
Thanks for the feedback. I'll share those excellent topics you suggested.
Very well explained and nice images as usual. Cheers.
Thanks for the feedback.
SPR中tap的位置，應該由CDR的鎖定條件來決定，不同的鎖定條件會造成ISI殘留量大小不同，不確定後續有沒有說明?
Hi Johnny, 非常感謝您的良好回饋。是的我同意。即使殘餘 ISI 不同，自適應 DFE 也應該能夠校準到正確的係數並正確消除。所以，我沒有強調這個微妙之處。
Hi, another very useful video :)
One question. At 11:21 you provide loop delay formula. I understood that TFB comes for H1 (or H2), TSUM is the summer settling time, TCK_Q is the slicer decision time (looking to first tap, which is the critical one). Basically TCK_Q is determined from the clock edge to the slicer output reaching let's say 90% .
However I don't understand what TSetup is, which you mention is sampler's setup time. As far as I know the clock and data are 90 degrees shifted with respect to each other. Is it possible that clock doesn't arrive exactly at 90 degrees shift and this creates additional delay which you denote as TSetup ? Thanks
Hi Hrachya, Thank you for the excellent question. Ideally, w/ the BB or MM CDR, that would be that clock should arrive exactly at 90 degrees. But, if the eye is not symmetric (on average), the BBPD (CDR) would make a shift slightly earlier or later. Similarly or more vulnerable in a MM (Baud-rate) CDR, the pulse response may cause the clock doesn't arrive exactly at 90 degrees shift. I hope those examples can provide insight into those subtleties.
@@circuitimage Thanks a lot for useful info. So, in conclusion the TSetup term in the delay formula is because the clock possibly can arrive not exactly 90 degrees phase shifted ?
@@hrachya_khachatryan You're very welcome. That's correct.
Thanks for your video, I have one question about error propagation in DFE, even burst error. For this disadvantage, we usually use THP precoding in PAM-4 mode. But why we seldom use this technique in NRZ mode? Is this related to DFE?
Hi Weili,
Nice to meet you and thanks for your excellent questions. You're correct. The PAM-4 has a much less margin (in eye width & eye height) than the NRZ; therefore, the precoding is necessary to mitigate the burst error, which is not very sensitive to NRZ in a DFE usage. You can refer to my other "why PAM4 & NRZ videos" to get more images of both signaling differences. 😉
想請問 除了上述原因導致不能單獨使用DFE 是不是也有一個原因是 在太高的Channel Loss (例如 30dB) 訊號本身的眼圖已經閉起來 並且無法正確判斷訊號的極性 導致DFE決策錯誤
Hi ZZZ,
Nice to meet you, and thank you for the good question.
You are correct.
With very high channel loss (e.g., 30dB), the signal's eye diagram can become closed, especially if the number of DFE taps is not large enough. In such cases, using only the DFE mode to equalize the 30dB loss would not be power efficient.
Thanks,
CC
@
Nice to meet you too. And thank you for your reply.
However, what I mean is that if the data itself cannot correctly distinguish between 1 and 0 under high channel loss, wouldn't this mean that even with a DFE with many taps, it still cannot be used because the decision is already incorrect which would cause error propagation.
Great videos but a quick question, why is error propogation not a big deal?
Thanks for the good question. The BER target is very small, e.g., < 1e-12 or 1e-15. Therefore, it's unlikely to be stuck from the error propagation if the DFE works in the beginning with a BER under the target.
Very well explained the topics and good attention seeking images.
@Srinivas Kalwad Glad you liked it!
Thanks for the great videos, can you please share all these slides with me?
@Naveen Kumar
Merry Christmas and Happy New Year! Thanks for the feedback and I'll provide an option for you.
@Circuit Image Thank you so much. Merry Christmas and Happy New Year, you too.