Sorry it took so long to answer this--wasn't expecting comments! The power problem mostly has to do with other logic that get their input from the "opposite" gate with PMOS devices in the pull-down and NMOS devices in the pull-up networks. Since the output of the "opposite" gate doesn't go all the way down to ground or all the way up to the supply voltage, the transistors of downstream gates may not turn all the way on or all the way off. This would result in some current flow in these downstream gates from the supply voltage to ground, since the transistors in both the pull-up and pull-down networks would be partially on.
Your explanation is simple and effective. It helps me understanding other related concepts too. Thank you, sir.
explaining with reasons behind the Vdd - Vth ( considering both gate source and drain potential would have been better )
Why can't nmos pull all the up to vdd....why can't pmos pull all the way down to vss
Thank you. You this video was really helpfull to me.
good job, thank you
How does it increases the power dissipation when connected opposite manner, can you pls explain ?
Sorry it took so long to answer this--wasn't expecting comments! The power problem mostly has to do with other logic that get their input from the "opposite" gate with PMOS devices in the pull-down and NMOS devices in the pull-up networks. Since the output of the "opposite" gate doesn't go all the way down to ground or all the way up to the supply voltage, the transistors of downstream gates may not turn all the way on or all the way off. This would result in some current flow in these downstream gates from the supply voltage to ground, since the transistors in both the pull-up and pull-down networks would be partially on.