Blocking vs Non Blocking Assignments In Verilog

In this Video I Discussed About Blocking and Non Blocking assignment in Verilog.
The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic. In software, all assignments work one at a time.
In a hardware description language such as Verilog there is logic that can execute concurrently or at the same time as opposed to one-line-at-a-time and there needs to be a way to tell which logic is which. Either
Nonblocking Assignment
Blocking Assignment

[@rahuljnanesh6390]

Wonderful 🥂

[@ExploreElectronics]

Good one. I have also tried this recently and uploaded in my channel..

[@PremChand-el6fh]

nice explanation