Im a PCB layout guy since 1990. Pisses me off that the EEs have taken my job because the software got easier and we became too expensive. Hopefully the EEs enjoy the extra workload and dont miss the highly skilled guys that used to do this stuff with their eyes closed. Long live the PCB Layout Guys.. Tiochaidh Ar La
There are still many companies that employ dedicated PCB layout experts, especially in large-scale consumer electronics, automotive, military and aerospace. And PCB designers who really understand signal and power integrity are in demand. Why not consider learning some SI/PI or RF skills? You can even do this with free access to many professional tools like Ansys EM desktop that has a free student version. Just a thought.
Hi, thank you so much for being on RUclips, I am an Electronics Engineer too, but there is a big gap in my career,and I want to learn designing to restart my journey. Happy to find you
Hi Ben, thanks for the video. Excellent point out for the via selection in Altium at 19:13. At 11:00 you mentioned preferred Via size is 508/305um. Have you considered here the minimum annular ring? I mean, 508-305 gives 203um, which means the annular ring in this case is only 101.5um. This is quite advanced, isn’t it? Maybe for next video you can point out, that for example the via hole size in Altium and later in Gerber files is the final via diameter after the board will be manufactured. However the manufacturer have to drill your via with bigger drill bit and in your case it would be probably 350um in order to make enough place inside the via's hole for the plating.
It's reasonably advanced yes, though in the video verbally I am telling people 20mil with 10mil hole is more standard today. I agree it would be very good to make a follow up about how vias are actually made in the factory and why it's important to maintain the minimum annular ring (which is another rule as well!!) DFM rules are always a welcome topic.
Evaluating AD2024 and the jumbo via is still being placed when selecting from the toolbar. Have you found a way to configure the default via dimensions?
Still confused about defining vias. When NOT using Net Classes, using Min/Max/Preferred is confusing. How does the software choose which via you want to place? If Min is 0.2mm, Max is 0.8mm, what will it choose and how will it choose it? I attempted to use the "Template Preferred" option in the Design Rule, and defined a via template library, but there seems to be no link between whats displayed in the design rule window and my via template. Basically I want to pre-define what vias are allowed in my layout, precisely, and then when choosing vias have only those vias be allowed. Documentation online is utterly confusing and following the steps listed to create a via template library and then use it does not work.
I agree about the documentation. The way it chooses depends on your preferences but the simplest way to control this is by hitting TAB while routing and use the NET Properties panel to select via size.... thanks for the question - I should make a video about this. Just to clear it all up... stay tuned! I will add that in much older versions of the software, there was nothing like a "pad stack" or pre-defined via. This was something OrCAD and PADS did, but not Protel/Altium. The only thing driving this was the design rules, and if you wanted a specific size you had to hit TAB and set it during interactive routing, and generally after doing that it would choose that size again next time.
Im a PCB layout guy since 1990. Pisses me off that the EEs have taken my job because the software got easier and we became too expensive. Hopefully the EEs enjoy the extra workload and dont miss the highly skilled guys that used to do this stuff with their eyes closed. Long live the PCB Layout Guys.. Tiochaidh Ar La
There are still many companies that employ dedicated PCB layout experts, especially in large-scale consumer electronics, automotive, military and aerospace. And PCB designers who really understand signal and power integrity are in demand. Why not consider learning some SI/PI or RF skills? You can even do this with free access to many professional tools like Ansys EM desktop that has a free student version. Just a thought.
This is likely the finest video on the internet.
That's very kind of you! Thanks.
Hi, thank you so much for being on RUclips, I am an Electronics Engineer too, but there is a big gap in my career,and I want to learn designing to restart my journey. Happy to find you
holly shit, the control+shift+mouse wheel tip is so useful! thanks so much
Good to see online Ben, thank you for sharing your Altium expertise.
Thanks Randy! Glad you found them!
Great tips, I have learned something new! Thank you!
Glad it was helpful!
Hi Ben,
thanks for the video. Excellent point out for the via selection in Altium at 19:13.
At 11:00 you mentioned preferred Via size is 508/305um.
Have you considered here the minimum annular ring? I mean, 508-305 gives 203um, which means the annular ring in this case is only 101.5um.
This is quite advanced, isn’t it?
Maybe for next video you can point out, that for example the via hole size in Altium and later in Gerber files is the final via diameter after the board will be manufactured.
However the manufacturer have to drill your via with bigger drill bit and in your case it would be probably 350um in order to make enough place inside the via's hole for the plating.
It's reasonably advanced yes, though in the video verbally I am telling people 20mil with 10mil hole is more standard today.
I agree it would be very good to make a follow up about how vias are actually made in the factory and why it's important to maintain the minimum annular ring (which is another rule as well!!)
DFM rules are always a welcome topic.
Very interesting. You mentioned a video on setting up design rules, is that still in the works?
Yes, please subscribe!
Evaluating AD2024 and the jumbo via is still being placed when selecting from the toolbar. Have you found a way to configure the default via dimensions?
Still confused about defining vias. When NOT using Net Classes, using Min/Max/Preferred is confusing. How does the software choose which via you want to place? If Min is 0.2mm, Max is 0.8mm, what will it choose and how will it choose it? I attempted to use the "Template Preferred" option in the Design Rule, and defined a via template library, but there seems to be no link between whats displayed in the design rule window and my via template. Basically I want to pre-define what vias are allowed in my layout, precisely, and then when choosing vias have only those vias be allowed. Documentation online is utterly confusing and following the steps listed to create a via template library and then use it does not work.
I agree about the documentation. The way it chooses depends on your preferences but the simplest way to control this is by hitting TAB while routing and use the NET Properties panel to select via size.... thanks for the question - I should make a video about this. Just to clear it all up... stay tuned!
I will add that in much older versions of the software, there was nothing like a "pad stack" or pre-defined via. This was something OrCAD and PADS did, but not Protel/Altium. The only thing driving this was the design rules, and if you wanted a specific size you had to hit TAB and set it during interactive routing, and generally after doing that it would choose that size again next time.
Ctrl + Shift + wheel scroll or just hit * on the numeric keypad - you're welcome !