Just gotta say, as someone who has gone through the universities and then into the industry. Your channel is probably the best channel for getting REAL practical application and useful knowledge for PCB design and I love how you present the simulations and use the extremes to show a point (i.e no via used vs the via fence - via fence not likely being realistic for an actual design I suspect but nonetheless proves the point quite fantastically). Appreciate what you do.
Wow, this just blew my mind!! I already knew and understood why you need stitching vias. But seeing it this way is just sooo interesting! It makes everything visually clear and straightforward. Thank you for this great simulation videos, you helped me a lot!!!
Great video! Also I think that it is interesting to add that in a four layer stackup TOP-GND-VCC-BOT if you have a critical signal over top and you must go to bottom, then the stitching via to gnd is not what you need. A capacitor VCC-GND close to the via will do the magic. You must consider that the polygon of the VCC net in VCC plane (poly because more than one voltage is ussualy needed so the plane has cuts) is over the portion of the track on bottom. I propose a simulation of this case for a future video. Best regards!
@Digital Nomad If you have two or three different supply voltages your VCC layer is not a solid plane, therefor can't be used as a return plane for signals on the bottom layer. Therefor I put the signals on layer 3 and put the power distribution on the bottom layer. Other option is go for a 6 layer board.
Try the coplanar waveguide (your fence) with minimal vias. This is typically how a coplanar waveguide is done and it would be interesting to compare the results.
Almost every single video of yours, there is something new to learn.. great work Robert, not many schools teach these.. I really like insights derived from your talk with Eric Bogatin and Rick Hartley
I just stumbled on this video, two years after you made it. Better late than never! Great video. I didn't expect the huge improvement from the GND via fence, so it was very educational! Thanks!
You may also want to investigate how multiple GND/PWR VIAs on decoupling capacitors impacts their effectiveness. Also, capacitor physical size. Great series of videos, thanks.
Your videos about PCB design are just amazing! I have watched most of your Altium tutorials and they were super helpfull. Thank you so much for your great work. I really appreciate it.
Could you do an example with some serial bus standards? Like SPI or SD for example, I'd like to see how the traces intefere with each other. Great video Robert!
Thanks for this. It's a very concise reference to point to, and makes what is technically complicated easy to understand. Not everyone has access to ADS, so I really appreciate this sort of content.
As always video was full of information, and today I learned something new about return currents because of you so thanks a lot. Keep sharing videos like this.
Great video! I would be interested to see simulations of different frequency signals and how the spacing of the stitching via effects the stray currents for the different wavelengths.
I think the reason for return currents to flow in other reference layers as well is due to the impedance of the return path. The reference plane directly under the signal will have the lowest impedance return path. But the subsequent reference planes will also have a return path impedance which is finite. The value of each return path is a function of frequency, dielectric height from the signal layer (as height increases, impedance increases) as well as the dielectric properties of the material and transmission line dimensions. You can think of each reference plane return path as parallel connected resistors (current is shared between resistors, but lower resistance values conduct more current). The first reference plane being Z1, the next being Z2 etc. So |Z1|
Thanks Robert, visualization is always great, exceptionally the last slide that compare all of them. Other people have suggest great things to try. 18min is also good length.
The simulation where you placed those ground tracks to completely shield the signal track is really cool. I remember when I was measuring cross talk between sensitive analog signals on an eeg amplifier, my senior engineer told me that if we use this trick in layout then the cross talk between adjacent channels will be close to 0. Thanks for showing me how that really looks like 👍.
More, than 10 years ago, when i worked on military factory, old womens, which work's in P-CAD spoke me about that thing. They didnt have SIpro, only P-CAD and own soviet expirience in electronics. Today I started to respect them even more.
@@RobertFeranec I would be interested in seeing different current strengths too, since it is both frequency and current that define how big of a mess it will be
I think the real reason why adding reflow vias can improve the signal quality is that the electromagnetic field tends to propagate along the space between a pair of parallel conductors.
Thanks Robert for the video. What I knew about these vias is that Altium has a tool called Vias Shielding, which allows you to create a track surrounded by vias so that it improves its characteristics. Greetings from Chile
Thank you a lot for that Video and the effort you are puting into it. At the moment this is my most favorit RUclips content and im looking everyday if something new was uploaded
The current penetrating to lower layer is probably visible this much because the color scale is saturated strongly in the upper layer. To see all values you could try logarithmic scale. I would be curious what is the actual ratio between the return current (density) on 1st and 2nd GND layer.
love your content . you should do one on how to handle a separate digital and analog ground planes. Such as where to attatch them, should it be close to source or close to a sensor? what if you only have a single layer board (without a ground plane)
In a good design there is no reason for different "types" of ground planes (e.g. "digital", "analog") other than for galvanic isolation. See works of Keith Armstrong (e.g. www.emcstandards.co.uk/files/part_4_planes_corrected_29_june_17.pdf)
Great series, Robert. It helped clarify a lot why some practices are done. In case you'd like to work on it, you seem to be pronouncing "Analysis" the same as "Analyzes" rather than /əˈnalɪsɪs/ .
The return current is like a displacement current as well so depending on the distance between layers which can define the capacitance between the layers, the return current can flow on layer 2 gnd plane and layer 4 gnd plane when crossing signals from layer 1 to layer 3.
Very informative video. Really learnt a lot. I think you can avoid the return currents in the other ground planes be adding stitching via along the length of the trace and not just at the point of transition.
You deserve big respect. I got a question. You simulated only with ground planes but what about power planes? Can you share more simulations including power planes and ground pour at top layer?
I think it makes sense that you see the currents following the tracks on the adjacent layers. The energy exists in the field between the signal trace and the reference plane, and that field is going to radiate outward a little - it won't be perfectly contained within the dielectric between layers.
Congrats, very nice video, thanks a lot for sharing, just to clarify; it seems the worst case is when you have the stitching via far away of the track transition, seems to be worst than the case without stitching via.
I really like these simulation videos to visualize what happens in different cases. It looks like care is taken to distill the example to really focus on the relevant concept. I'd be interested to see a video on ground pour sections that only have one via in them, or have a long "finger" that isn't stitched at the end. I try to avoid this on my designs, and fix it where I see it, but I'm not sure how bad it is, and how much time I should spend on it.
Very nice visualisation of why via stitching is so important. I do wish the simulation would show the field strength inside the dielectric, rather than just the current in the copper. At high frequncies, the energy is in the dielectric not in the copper.
Great simulation, thank you. Here is a question in my mind. Let's think it is a four layer system. Signal, Ground, Power, and Signal. How does the return signal look, and what are the possible solutions?
Thank you for the wonderful simulation. just wondering, if you had done the same simulations with 1Hz signal or way upto 1GHz signal! if yes could you share the comparative slide? thanks for the share
This is confusing. I don't know if you will comment on this but here is the confusion; what I learned is that signal lines must end up to the gnd after reaching components. So for example power --- Component --- GND. And in your video, for third layer pcb you said you dont need gnd stitching vias. This sound like Power --- component and done. Also, for initial simulation, there seems there is only Power--- component And no connection from component to ground.
Great videos, should see how those return currents affect cross-talk between lines. Even if two signal lines are well spaced, can a badly spread out ground current add noise? Can limiting the ground currents reduce EMI? Obviously, but how many vias will it take? A fun example, but something we should never do, would be a pwm signal next to an important analog signal line.
Adding the ground fence does add a lot of distributed capacitance, in turn affecting the input impedance of the line. That change in impedance will change how the input signal couples into the line. The channel host can correct me here, but ADS’s ports are probably set to be matched, so the input power was consistent in the two the simulation. Also, at 1MHz the change is probably small, but the simulation could easily give us that change in Zin.
Late to the party, but really nice video Robert! Haven't seen similar simulations before, but I often via stitch like the last example. So that feels good :) Great video!
Dear robert, Thanks for posting your video. I learn PCB design with your videos. I want learn also keysight software how to convert then upload the PCB files in keysight then how to change the options. I need clear videos for keysight using please post a video
Thanks for the nice simulations, It would be interesting If you did a simulation to see what happens when adding stitching VIAs in the case when the return currecnt flowed in multiple layers.
Thank you for your nice video! Can you please how to import the PCB layout of Altium to Keysight ADS? I want to check my own PCB layouts with regard to the current path. And one more question! What is the difference between Ansys and Keysight ADS?
Thank you Robert for the great video. Could you do a video on impact of sandwiched signal (perfect strip line ) model VS one side Ground and other side split plane signal ? Thanks in advance
redo, but use bypaass caps instead of vias. It is common to run traces one direction on one layer, then route perpindicular traces on another layer. The layers aren't necessarily all ground. A power plane is typical. This is why you should sprinkle bypass caps around the board, EVEN AWAY from components. This is also why you should bypass unused power signals on connectors. The cable references some current to power signals.
Very very nice and helpfull video, like always :) I think should be interesting to see how the system response in different frequency range and with different distance between stitching vias and point where signal change layer. Also with a stitching vias near the point where is the current source and current sinking. Also, i dont know if this simulation are in sinusoidal waveform, but i think should be interesting to see if the return current and stitching vias are affected if the signal are squarewave and with different rise/fall time, like the EMI level are.
"stitching vias near the point where is the current source and current sinking." I believe Robert's using through-hole connector pins at source and load, which are connected to all planes of the same net -- specifically the ground pin at each connector is connected to all ground layers.
In previous videos Robert showed similar simulations at different frequencies. With square waves, the different frequencies "composing" the square wave will have return current paths that follow the signal track to different degrees.
Finally real simulations / answers from someone who designs real world PCB's! Thanks!
Thank you very much Danny
Just gotta say, as someone who has gone through the universities and then into the industry. Your channel is probably the best channel for getting REAL practical application and useful knowledge for PCB design and I love how you present the simulations and use the extremes to show a point (i.e no via used vs the via fence - via fence not likely being realistic for an actual design I suspect but nonetheless proves the point quite fantastically). Appreciate what you do.
Thank you very much
Wow, this just blew my mind!! I already knew and understood why you need stitching vias. But seeing it this way is just sooo interesting! It makes everything visually clear and straightforward. Thank you for this great simulation videos, you helped me a lot!!!
Thank you
Great video!
Also I think that it is interesting to add that in a four layer stackup TOP-GND-VCC-BOT if you have a critical signal over top and you must go to bottom, then the stitching via to gnd is not what you need. A capacitor VCC-GND close to the via will do the magic. You must consider that the polygon of the VCC net in VCC plane (poly because more than one voltage is ussualy needed so the plane has cuts) is over the portion of the track on bottom. I propose a simulation of this case for a future video. Best regards!
Thank you Santi. PS: I have this on my list to simulate it. Some other people also would like to see it.
TOP - GND - SIG - PWR is my preferred setup, normally have more than one VCC
@Digital Nomad If you have two or three different supply voltages your VCC layer is not a solid plane, therefor can't be used as a return plane for signals on the bottom layer. Therefor I put the signals on layer 3 and put the power distribution on the bottom layer. Other option is go for a 6 layer board.
@@sparqqling L1 and L2 are close together, however L2 and L3 have generally more than 1mm prepreg inbetween
@@RobertFeranec I am looking forward to this “with 4 eyes” 👀
very good simulation, nice and clean.
Try the coplanar waveguide (your fence) with minimal vias. This is typically how a coplanar waveguide is done and it would be interesting to compare the results.
1/10 lambda spacing would be plenty enough. The amount of vias he used is a bit of over kill for the simulated 10k ~ 300M frequencies
gnd via fence is called grounded coplanar waveguide. It's used a lot in RF designs
You manage to clarify concepts that other people seem determined to obscure. Well done. Thanks!
Thank you C B
Almost every single video of yours, there is something new to learn.. great work Robert, not many schools teach these.. I really like insights derived from your talk with Eric Bogatin and Rick Hartley
Thank you Srudeep
I just stumbled on this video, two years after you made it. Better late than never! Great video. I didn't expect the huge improvement from the GND via fence, so it was very educational! Thanks!
You may also want to investigate how multiple GND/PWR VIAs on decoupling capacitors impacts their effectiveness. Also, capacitor physical size. Great series of videos, thanks.
Your videos about PCB design are just amazing! I have watched most of your Altium tutorials and they were super helpfull. Thank you so much for your great work. I really appreciate it.
Could you do an example with some serial bus standards? Like SPI or SD for example, I'd like to see how the traces intefere with each other. Great video Robert!
Thanks for this. It's a very concise reference to point to, and makes what is technically complicated easy to understand. Not everyone has access to ADS, so I really appreciate this sort of content.
Thank you very much VejyMonsta
As always video was full of information, and today I learned something new about return currents because of you so thanks a lot. Keep sharing videos like this.
Thank you Robert for simple lunguage explanation! The latest simulation shows like you fence the signal like in coaxial cable.
Thank you so much. This is exactly what I am looking for. I was wondering how a guard ring for rf pcb works. But I understand how it work visually.
Excellent explanation. Thank you.
Best explanation, appreciate your efforts
I really appreciate that you addressed the topic I suggested some time ago. Kudos!
Thank you Lukas
Big thumbs up! Very interesting video. I really enjoy these real life examples, explained in a way I can understand. You're a good teacher!
Thank you very much.
Hello Sir, Could you make the same for differential pair signals..
Great video! I would be interested to see simulations of different frequency signals and how the spacing of the stitching via effects the stray currents for the different wavelengths.
I think the reason for return currents to flow in other reference layers as well is due to the impedance of the return path. The reference plane directly under the signal will have the lowest impedance return path. But the subsequent reference planes will also have a return path impedance which is finite. The value of each return path is a function of frequency, dielectric height from the signal layer (as height increases, impedance increases) as well as the dielectric properties of the material and transmission line dimensions. You can think of each reference plane return path as parallel connected resistors (current is shared between resistors, but lower resistance values conduct more current). The first reference plane being Z1, the next being Z2 etc. So |Z1|
This video is so helpful. Thank you!
Thanks Robert, visualization is always great, exceptionally the last slide that compare all of them. Other people have suggest great things to try. 18min is also good length.
The simulation where you placed those ground tracks to completely shield the signal track is really cool. I remember when I was measuring cross talk between sensitive analog signals on an eeg amplifier, my senior engineer told me that if we use this trick in layout then the cross talk between adjacent channels will be close to 0. Thanks for showing me how that really looks like 👍.
Thank you Nihar
More, than 10 years ago, when i worked on military factory, old womens, which work's in P-CAD spoke me about that thing. They didnt have SIpro, only P-CAD and own soviet expirience in electronics. Today I started to respect them even more.
I'd like to see a continuation of this video, where you sweep or step the frequency from VLF to SHF bands. If that's possible in ADS anyway.
Like to see different freq down the 0mhz.
Good idea. I am making a note, I can try that in some future videos.
Agreed, seeing how various frequencies compare would be really interesting. Thank you for your videos Robert! They really are enlightening!
@@RobertFeranec I would be interested in seeing different current strengths too, since it is both frequency and current that define how big of a mess it will be
Great work as usual Robert! Thoroughly enjoy those videos
Thank you very much Bannay
Thanks for this simulation it is really useful
Wow robert. It is always such a treat to watch your videos... Thanks you.and please continue and inspire us more.
it took me a while to figure out 'written' current is actually a return current ))
Great video! Thanks for serving this tremendously useful knowledge on a platter!
Thank you for this video.
I think the real reason why adding reflow vias can improve the signal quality is that the electromagnetic field tends to propagate along the space between a pair of parallel conductors.
Real simulation explains well :)
Thanks Robert for the video. What I knew about these vias is that Altium has a tool called Vias Shielding, which allows you to create a track surrounded by vias so that it improves its characteristics. Greetings from Chile
Thank you Leonardo
Thank you a lot for that Video and the effort you are puting into it.
At the moment this is my most favorit RUclips content and im looking everyday if something new was uploaded
Thank you very much white test for very nice words
The current penetrating to lower layer is probably visible this much because the color scale is saturated strongly in the upper layer. To see all values you could try logarithmic scale. I would be curious what is the actual ratio between the return current (density) on 1st and 2nd GND layer.
love your content . you should do one on how to handle a separate digital and analog ground planes. Such as where to attatch them, should it be close to source or close to a sensor? what if you only have a single layer board (without a ground plane)
In a good design there is no reason for different "types" of ground planes (e.g. "digital", "analog") other than for galvanic isolation. See works of Keith Armstrong (e.g. www.emcstandards.co.uk/files/part_4_planes_corrected_29_june_17.pdf)
very informative, especially the chart at the end!
Great video! It might be interesting to see this with a differential pair.
Very good idea. I made a note about this. Thank you
Very simple and good explanation! Thanks a lot, Robert
Thanks Robert, a very instructive video.
Well done!
I found my new wall calendar's picture... (The one at the end of video !) Thank you a lot Robert
:)
Great series, Robert. It helped clarify a lot why some practices are done.
In case you'd like to work on it, you seem to be pronouncing "Analysis" the same as "Analyzes" rather than /əˈnalɪsɪs/
.
Thank you very much Tom
The return current is like a displacement current as well so depending on the distance between layers which can define the capacitance between the layers, the return current can flow on layer 2 gnd plane and layer 4 gnd plane when crossing signals from layer 1 to layer 3.
Very informative video. Really learnt a lot. I think you can avoid the return currents in the other ground planes be adding stitching via along the length of the trace and not just at the point of transition.
Another very informative simulation -- thanks Robert!
Thank you Graham
Always best videos. Thank you again. I learn always with your videos.
Thank you very much Freddy
The two ground planes above and below the track are just two capacitors in parallel so the return current of 1MHz signal is on both of them.
Another useful video, as usual, your videos always make to learn something new sir, thanks for sharing your knowledge.
Thank you Haribabu
You deserve big respect. I got a question. You simulated only with ground planes but what about power planes? Can you share more simulations including power planes and ground pour at top layer?
great! It's easy to understand. I'll use many stitching VIAS.
Thank you
Thank you!
Thanks for the Video!
Thank you
I think it makes sense that you see the currents following the tracks on the adjacent layers. The energy exists in the field between the signal trace and the reference plane, and that field is going to radiate outward a little - it won't be perfectly contained within the dielectric between layers.
Thank you so much,Robert It's very useful.
Great video!
Congrats, very nice video, thanks a lot for sharing, just to clarify; it seems the worst case is when you have the stitching via far away of the track transition, seems to be worst than the case without stitching via.
I really like these simulation videos to visualize what happens in different cases. It looks like care is taken to distill the example to really focus on the relevant concept.
I'd be interested to see a video on ground pour sections that only have one via in them, or have a long "finger" that isn't stitched at the end. I try to avoid this on my designs, and fix it where I see it, but I'm not sure how bad it is, and how much time I should spend on it.
The vias along the entire track is effectively creating a conduit/ coax feed of the track.
Very nice visualisation of why via stitching is so important.
I do wish the simulation would show the field strength inside the dielectric, rather than just the current in the copper.
At high frequncies, the energy is in the dielectric not in the copper.
Thank you Nicholas. PS: I asked Keysight if I could play also with their RF 3D field simulator ... let's see ....
Nice Robo. But try 1 stiching via at 100MHz with comparing to 1MHz. I think that next ground-plane current will be much lover in higher frequencies.
Great video and many thanks for sharing. It would be nice if you also simulate the cases where 1 and 3 vias on the other side of the signal track.
Great job!
Thank you Yarmela
This was very helpful! Can you help understand how return currents are affecting performance?
Great simulation, thank you. Here is a question in my mind. Let's think it is a four layer system. Signal, Ground, Power, and Signal. How does the return signal look, and what are the possible solutions?
Thank you for the wonderful simulation.
just wondering, if you had done the same simulations with 1Hz signal or way upto 1GHz signal! if yes could you share the comparative slide?
thanks for the share
Very helpful! thanks for it :)
Thank you
Thank you a lot
This is confusing. I don't know if you will comment on this but here is the confusion; what I learned is that signal lines must end up to the gnd after reaching components. So for example power --- Component --- GND. And in your video, for third layer pcb you said you dont need gnd stitching vias. This sound like
Power --- component and done. Also, for initial simulation, there seems there is only
Power--- component
And no connection from component to ground.
Nice Vids Very Helpfull
Great videos, should see how those return currents affect cross-talk between lines. Even if two signal lines are well spaced, can a badly spread out ground current add noise? Can limiting the ground currents reduce EMI? Obviously, but how many vias will it take? A fun example, but something we should never do, would be a pwm signal next to an important analog signal line.
Some effects of crosstalk and coupling are visible in this simulation: ruclips.net/video/4nEd1jTTIUQ/видео.html
Thanks!
Hi, very informative video. Can you try a video with a series component (AC cap) with and without void.
very interesting and useful video. Could you make a video described how to insert stitching via in polygon?
Really enjoying your vids. Thanks!
Thank you Oguzhan
The fence reminds me of a coaxial cable. Does it add capacitance that affects the signal? BTW thanks very much for these videos.
Thank you Roger
I would have to imagine so, you could see that those ground traces next to it in the final example had a ton of current flowing through them
Adding the ground fence does add a lot of distributed capacitance, in turn affecting the input impedance of the line. That change in impedance will change how the input signal couples into the line. The channel host can correct me here, but ADS’s ports are probably set to be matched, so the input power was consistent in the two the simulation. Also, at 1MHz the change is probably small, but the simulation could easily give us that change in Zin.
Late to the party, but really nice video Robert! Haven't seen similar simulations before, but I often via stitch like the last example. So that feels good :) Great video!
Thank you Chris
Enjoyed even for an ME like me.... thank you!
Thank you Joseph
Your videos are very practical and have been very helpful.
I just purchased your udemy courses as well. Thank you!
Dear robert,
Thanks for posting your video. I learn PCB design with your videos. I want learn also keysight software how to convert then upload the PCB files in keysight then how to change the options. I need clear videos for keysight using please post a video
I think, via should help even with simple board.
Very interesting content. I think the videos could be more concise though, I think this would have made a better 10 minute video.
Make a power point presentation also. It will help you to review it easily.
Thanks for the nice simulations, It would be interesting If you did a simulation to see what happens when adding stitching VIAs in the case when the return currecnt flowed in multiple layers.
Thank you for your nice video! Can you please how to import the PCB layout of Altium to Keysight ADS? I want to check my own PCB layouts with regard to the current path.
And one more question! What is the difference between Ansys and Keysight ADS?
Thank you Robert for the great video. Could you do a video on impact of sandwiched signal (perfect strip line ) model VS one side Ground and other side split plane signal ? Thanks in advance
I didn't know this. Thank you!!
:)
thanks
redo, but use bypaass caps instead of vias.
It is common to run traces one direction on one layer, then route perpindicular traces on another layer.
The layers aren't necessarily all ground. A power plane is typical.
This is why you should sprinkle bypass caps around the board, EVEN AWAY from components.
This is also why you should bypass unused power signals on connectors. The cable references some current to power signals.
Very interesting thank you Robert
Thank you Gharbi
Very nice to share all this with us, Thanks a lot. One question, is ground vias necessary for small signal (logic) ?
Excellent visual demonstration. Is there a way you could do a video on a guard trace with simulation
Very very nice and helpfull video, like always :) I think should be interesting to see how the system response in different frequency range and with different distance between stitching vias and point where signal change layer. Also with a stitching vias near the point where is the current source and current sinking. Also, i dont know if this simulation are in sinusoidal waveform, but i think should be interesting to see if the return current and stitching vias are affected if the signal are squarewave and with different rise/fall time, like the EMI level are.
Thank you very much Luca PS: I am not sure if it is possible to set waveform shape. I will ask Keysight
"stitching vias near the point where is the current source and current sinking." I believe Robert's using through-hole connector pins at source and load, which are connected to all planes of the same net -- specifically the ground pin at each connector is connected to all ground layers.
In previous videos Robert showed similar simulations at different frequencies. With square waves, the different frequencies "composing" the square wave will have return current paths that follow the signal track to different degrees.
Ok! ok! here's a comment :p (great job btw)