Hi Robert This is a fantastic video! Many thanks for taking the time to create this video and taking the time to explain what "via in pad" technology is, how it is created and what to look out for. I initially made the assumpton that one simply placed a via in the pad and that was the end of it. Boy was I surprised to learn what the technology was and all the rules that surround it are. Many thanks and please keep these videos coming, I can confirm that they are serving me well and are well worth the time watching. Regards, Sean
There are other advantages. By using via and pad, and other micro via techniques, you can keep your ground and power planes basically solid everywhere, including just under BGA packages. This improves a EMC a lot, by doing shielding, and providing better current paths where it is needed. It also makes the stackup more symetric, and prevent board warping. It also make a great distributed capcitor, and with proper type of layer / prepreg, it can provide substantial capacitance (few nF per cm^2), which can make it possible to get rid of a lot of MLCCs. In the end it is possible to reduce number of layer due to these combined effects, and flexibility.
Omg Robert, this is a great great video. I already a big fan of your work. However, this kind of very detailed videos about a single topic are something else. After I watch a video like this I feel like a totally level up in hardware design and this kind of information is really hard to get by ourself.
very well done presentation , helped with the understanding the finer details of doing a via in pad and how it can affect the PCB manufacturing stage and what needs to be taken into account for the assembly stage without potentially creating undesired issues
Thanks Robert. I'll probably be coming back to watch parts of this one again when I'm doing something specific with microvias or via in pads. Also a lot of good information about how they have to fabricate the vias with either resin or copper filled and when to use each. Very useful info!
Yes, I was thinking if to include also additional information around VIA in PAD, but I also found it interesting and important to understand the process so I decided to include it. I am very happy you noticed that. Thank you Doug.
Very informative. Just moving into higher density PCBs, so much needed info for us. I also like how you bring in experts as "clips" into your postings. Thanks!
excellent video. Very detailed information. Absolutely thoroughly done! What a wonderful spokesman you were able to interview from exception pcb.. he seemed to have every aspect of his business down to the micron in memory on demand. I'm sure this company is incredibly good at what they do!
Loved the video and call! It seems like via-under pad is the best solution to get those traces out from under the bga. The question is now, how to do it effectively while keeping mind Rick Hartley’s rules of thumb for EMI. 🤔
Same as @Hemal... just in time for my new design. Due to the 60% cost mentioned, I might have to try simple micro VIAs first before using VIA in pad. Confirmed this cost with two manufacturers, seems accurate enough. Thanks @Robert!!
Very goooood video, these types of videos are very helpful... they help us to better understand the industry to improve our design skills. Muchas Gracias Robert.
Hi Robert, very useful and great job, your approach to bringing manufacturers in touch with PCB designers is a great help to design better PCBs. There is another subject that may some engineers like to know about is the "Embedded Component " PCB design. Thank you for all your hard works and wonderful training Videos.
Thanks Mr. Feranec great video again. I heard from some youtuber that backdrilling is a method to avoid stubs where you want to use through hole vias instead of uvias for the sake of lower cost. If you have experience about that you can make a video telling what type of design tricks we can use to reduce PCB cost and production time and still get the best performance.
Thanks Robert, great job again! Watching you speaking about the sliver I had to think about a video dealing with the pros and cons of soldermask defined pads - just in case you're looking for new ideas.
Thank you Marcus. I have been thinking about soldermask defined pads (and I actually asked some questions during the call), but the result was - not clear, so I have not included it in this video. Basically, for now I decided, that if I am still able to go with standard pads, I will use them and only go for soldermask defined pads if there is no other way (decision based on my video about footprints: ruclips.net/video/cMxXea16Hxc/видео.html )
Very nice, Robert! Lots of good info here. I've got some very limited exposure to via in pad designs that a colleague did. We worked together for about a year and a half. One thing to consider with via filling in general, is the electrical performance gain when the via is filled with metal (copper, or sometimes solder). Also, via in pad isn't just for enabling signal escape for BGA packages. It also allows very compact placement of chip components. With VIP and a couple extra layers, you can place all the components on the PCB right next to each other, with few limitations.
On their current "capabilities" page they provide different aspect ratios: standard processing: 0.5:1, advanced processing: 0.75:1. They also offer some other microvia techniques, and you need to contact them to get more details.
Very useful video. Thank you, Robert. I have to add that using micro vias on top of each other is not an issue ( n most cases) but putting micro vias on buried Vias is not a good idea. Also when using Altium, crossing plane layers with micro vias will result in an error of not having a pad in the plane layers (this is a software issue by Altium). the solution is to using a signal layer instead of a plane layer and filling the layer with a polygon.
This was is a very helpful video. Thank you. I would very much like to see a follow-up video about the board stack-up you illustrated, and how to maintain the correct track impedance for signals that use staggered micro-vias on the outer two layers, then a signal layer below that, and only then a (ground) plane layer below that. If the wave is in the dielectric material between the trace and the ground plane, how do we calculate the requirements with staggered micro-vias layers that each have different distances from the nearest ground plane. For example, do we need different trace widths on each layer to maintain a consistent impedance.
Thank you very much Nicholas for your feedback. For the designs I have done, I have not been thinking to much about impedance in VIA (there is not really much what I can do about that). The same is about the very short tracks on L2 (not really many options what to do with these). However, if I will have a chance to design a very high speed boards, I will make a video about that.
Robert , at end you forget to have tear drop on via , all via should have tear drop , special those Microvia , and suarly all through hole via , this is the way I do , P.S. Altium can also generate via drill hole file per layer too , for easy manufacturing
You can use longer microvia, i.e. from layer 1 to 3, instead of going from 1 to 2, then moving to different place, then 2 to 3. They will be made as 1 to 2, and from 2 to 3, and aspect radios between each layer will be fine. You might want to enlarge the ring size a bit on the layer 2, to ensure the proper registration, but it shouldn't be a problem, especially if the 2 to 3 is the copper filed via. Basically building a taller via in two steps, as a tower. However, you need to check with the manufacturer how to do it.
Hello. I have some interesting board this is NanoPi NEO-LTS . It's interesting because that board has allwinner h3 chip with 0.65 mm pitch and it's some how routed on 4 layers pcb!!!(you can check out this on theirs web site) I am unsoldered processor and ddr3 memory and discover that they break most of the rules that recommended in design guides, distance between positive and negative trace of differential pair same as distance to other traces and it's about one trace width. But It's actually works fine. And Yes they place vias between pads.
I think you get it reverse in the cost analysis. If you make a big PCB, or big panel, it will cost you relatively less. If you are making a single small board, then it will relatively cost you way more.
I meant if you use the same technology. For example, if you us all the uvias and buried vias etc, then bigger PCB is going to be a very expensive, comparing to a small one. On a small PCB you can use almost any technology and it is almost always going to cost just a couple of dollars for higher quantities.
@44:40mins I thought you couldn't go from layer 1 to layer 3 because of the fabrication process. They glue boards together and then drill through the stack. So, you could go from layer 1 to layer 2, or layer 1 to layer 4, but not layer 1 to layer 3. Sorry if that is not clear.
Hi Robert, very helpfull video. You shared a lot with me Thank you. You can use Draftsman documentation in Altium for board specification and drill table.
Hi Robert, I don't agree about via definition at first 10minutes. You have forgotten on plating thickness for through hole via. If we define hole of via in altium of 0.15mm this is the finished plated hole. However the manufacturer have to drill via with 0.2mm bit in order to have of 25um copper on vias wall. Next, we have IPC standard an minimum anular ring. For standard process they require 125um in oder to avoid brake out on ring. It yields 150um + 2x25um + 2x125um is 450um outer diameter of via. So it means, we have to know the drill they will use for mnf. process in order to provide reliable plating. Another question, have you found how define vias in altium which should be plugged according type VII. For example, we had via and soldering pad both had diameter of .0.6mm. In altium drill file they have been marked with same symbol T4= 0.599mm. Pcb manufacturer pluged at the end everything, both vias and pads. How avoid this ib future? Br Josko
Hi Robert, first of all, thanks for this video, congratulations on the 30k subscribers and thanks for your HARDWARE DESIGN TIPS series. I learned so much from them for my first big PCB. Maybe we get another 25 videos in this series now that you have reached 30k subscribers!?! Regarding the documentation of what vias should be copper or resin filled, you might take a look at draftsmen. With it you can document your board stack including drill/layer pairs and/or backdrilling, ... and you can add textual comments. Whether it is able to highlight those vias which have to be filled, I currently cannot check but I think so. Draftsmen is a pretty good tool and advanced in the last versions of AD compared to its feature set when it was release with (I believe) AD15. Check it out. Thanks and please let us participate on your knowledge and experiences in the future. Stay healthy! Tobias
Thank you very much Tobias. I am very happy that you found the videos helpful. PS: I will have a look at possibilities in Draftsman. I was looking into PCB, as often for PCB manufacturing I place everything into gerbers, so people processing the gerbers see also all the manufacturing notes in one place together with layers.
Robert, I have a question. If you do not use uvia stacked (top of each other), but go sequentially stepwise (staggered via) TOP - Layer2(GND) - Layer3(Signal). In this case, the Layer2 will have a short piece of track that will not have a reference layer. I think this is the same as drawing a track over a gap in the reference layer. ? Or not? (43:35 timing)
Hi Robert Feranec, Very informative video, I learnt alot about VIA ON PAD, plugging and filling. Thanks alot for your selfless helping effort. You mentioned in the video, that you change the via size to 0.201mm for copper filled via and highlight in other document that 0.201mm vias are the copper filled ones. Instead, we can use the description column in the drill table to indicate that 0.201mm vias are copper filled ones ? Is it possible ? Regards, Naveen
Well done, thank you!. I think you said you felt uncomfortable in using the 0.350mm via as a through-hole via between pads (in a dog-bone configuration), yet it sounded like you were going to use that same via in the middle of the processor pad in a "via in pad" configuration. Why do you feel that the 0.350mm via is too small for the first configuration, but acceptable for the other?
Yes, that is right. We often pay between $3000 - $5000 USD. But they need to manufacture whole panel, so if your board is small you can get 15 boards for almost the same price as 5 boards.
Thanks a lot Robert, very useful video again ! I wonder that via size can be smaller than BGA pads ? Is there any problem about that. For example: 0.5 mm BGA pad and 0.35 mm via (via has 0.15 mm hole size) on this BGA.
Mmm, if we dont fill microvia with neither copper nor epoxy, and the microvia is small enough, will the tin ball from the bga be sucked through the microvia?, perhaps it won't because of the big viscosity of the molted tin. It could be a cost effective solution.
I have used a 100um microvia hole in a 400um BGA pad without filling and no problems in SMD. There may be a bubble in there but problems have not shown up.
Hi Robert I have a beginner doubt on solder mask expansion. What does it stand for? Does it mean solder resist is not applied in the area of solder mask expansion? That’s what I understood from the last part of the video. That if the expansion makes the sliver too small solder bridges may form between adjacent pads. Am I correct in this understanding?
Hi Robert. Please can you show the layout of a simple power net, say +5v and gnd, nothing complex, best practise for the symbols and the net names. i struggle with how to set them up and i always have errors after compiling. I use altium V17. Many thanks in advance. Be safe in these trying times.
I have some of tutorials for older Altium ( welldoneblog.fedevel.com/2012/04/27/6altium-tutorials-for-newbies/ ), but what you can find useful may be actually number of videos I created about designing boards (browse through the search results, maybe you will find something interesting): welldoneblog.fedevel.com/?s=starting
Robert, sometimes I see you put via close to smd pad at Altium. In this case, you change rules ? usually I send boards to JLCPCB and they are some constraints using via close to pads
very useful information indeed! Thank you Robert. So, the inforamtion about via-filling that I understood is like this: to have copper-filled through-hole vias, one has to explicitly tell the PCB manufacturer to do that and there is no direct way to specify that in Altium. Is this correct?? Also for larger power devices like MOSFETs, can the vias-in-pad be defined in the footprint library itself?? Or shall one use it only in the PCB?
No, you can't specify it in Altium. Simply use an unique hole dimension for the vias which are going to be filled so you can simply list them and tell the manufacturer that these are the vias you would like to fill. PS: you can define them in library, but do not forget to include these vias in the list of filled vias.
A lot of information, thank you so much Robert. I have a question for you. When we should use dog-bone fanout over via in pad or vice versa? Dogbone fanout is used because it is cheaper? Canberk
Thanks for the video Robert, very interesting! I wonder if you know if there is any upper limitation in drillsize when doing copper filled vias for use as thermal vias? BR Tomas
I was also trying to same. Also the reason for me to watch this video to handle the fanout for 0.4 pitch BGA. After watching the video i decided that only possible solution is using via-in-pad with filled or caped vias and PCB needs to be at least 6 layers. Blind(L1-L2) and burried vias (L2-L3) has to be used because of 0.1mm hole size. I also talked to my friends who have experience in PCB assembly. They said it is more complex and more expensive. In my design there was only one component like this. I watched the video to learn how to use via-in-pad. After watching it i decided not to use 0.4mm package and change it to QFN.
Hi Robert
This is a fantastic video!
Many thanks for taking the time to create this video and taking the time to explain what "via in pad" technology is, how it is created and what to look out for. I initially made the assumpton that one simply placed a via in the pad and that was the end of it. Boy was I surprised to learn what the technology was and all the rules that surround it are.
Many thanks and please keep these videos coming, I can confirm that they are serving me well and are well worth the time watching.
Regards,
Sean
Great timing! I'm currently working on a design that uses via in pad.
Thank you for your work Robert, we really appreciate it.
I am very happy you found it useful
There are other advantages. By using via and pad, and other micro via techniques, you can keep your ground and power planes basically solid everywhere, including just under BGA packages. This improves a EMC a lot, by doing shielding, and providing better current paths where it is needed. It also makes the stackup more symetric, and prevent board warping. It also make a great distributed capcitor, and with proper type of layer / prepreg, it can provide substantial capacitance (few nF per cm^2), which can make it possible to get rid of a lot of MLCCs. In the end it is possible to reduce number of layer due to these combined effects, and flexibility.
Omg Robert, this is a great great video. I already a big fan of your work. However, this kind of very detailed videos about a single topic are something else. After I watch a video like this I feel like a totally level up in hardware design and this kind of information is really hard to get by ourself.
Thank you Burak
very well done presentation , helped with the understanding the finer details of doing a via in pad and how it can affect the PCB manufacturing stage and what needs to be taken into account for the assembly stage without potentially creating undesired issues
Thanks Robert. I'll probably be coming back to watch parts of this one again when I'm doing something specific with microvias or via in pads. Also a lot of good information about how they have to fabricate the vias with either resin or copper filled and when to use each. Very useful info!
Yes, I was thinking if to include also additional information around VIA in PAD, but I also found it interesting and important to understand the process so I decided to include it. I am very happy you noticed that. Thank you Doug.
Thanks Robert. I am just needing this info for my design. Started learning and thanks for all your information.
Thank you very much Sapam
Very informative. Just moving into higher density PCBs, so much needed info for us. I also like how you bring in experts as "clips" into your postings. Thanks!
excellent video. Very detailed information. Absolutely thoroughly done! What a wonderful spokesman you were able to interview from exception pcb.. he seemed to have every aspect of his business down to the micron in memory on demand. I'm sure this company is incredibly good at what they do!
Thank you so much sir...
All information on this video have for #Via & #Pad....Every one should see this video...
Loved the video and call! It seems like via-under pad is the best solution to get those traces out from under the bga. The question is now, how to do it effectively while keeping mind Rick Hartley’s rules of thumb for EMI. 🤔
Same as @Hemal... just in time for my new design. Due to the 60% cost mentioned, I might have to try simple micro VIAs first before using VIA in pad. Confirmed this cost with two manufacturers, seems accurate enough. Thanks @Robert!!
Very goooood video, these types of videos are very helpful... they help us to better understand the industry to improve our design skills. Muchas Gracias Robert.
Thank you very much Diego for nice words.
Robert, your videos are fantastic!
Thank you very much Caleb
Hi Robert, very useful and great job, your approach to bringing manufacturers in touch with PCB designers is a great help to design better PCBs.
There is another subject that may some engineers like to know about is the "Embedded Component " PCB design.
Thank you for all your hard works and wonderful training Videos.
Thanks Mr. Feranec great video again. I heard from some youtuber that backdrilling is a method to avoid stubs where you want to use through hole vias instead of uvias for the sake of lower cost. If you have experience about that you can make a video telling what type of design tricks we can use to reduce PCB cost and production time and still get the best performance.
I have not used backdrilling yet (most designs we do have to be cost optimized)
Thanks Robert, great job again! Watching you speaking about the sliver I had to think about a video dealing with the pros and cons of soldermask defined pads - just in case you're looking for new ideas.
Thank you Marcus. I have been thinking about soldermask defined pads (and I actually asked some questions during the call), but the result was - not clear, so I have not included it in this video. Basically, for now I decided, that if I am still able to go with standard pads, I will use them and only go for soldermask defined pads if there is no other way (decision based on my video about footprints: ruclips.net/video/cMxXea16Hxc/видео.html )
Very nice, Robert! Lots of good info here. I've got some very limited exposure to via in pad designs that a colleague did. We worked together for about a year and a half. One thing to consider with via filling in general, is the electrical performance gain when the via is filled with metal (copper, or sometimes solder). Also, via in pad isn't just for enabling signal escape for BGA packages. It also allows very compact placement of chip components. With VIP and a couple extra layers, you can place all the components on the PCB right next to each other, with few limitations.
Thank you Greg for your feedback.
Hi Robert, Great video, wonderful details technical, brilliant idea bring manufacture Mike playing calling, thank you very much for the excellent job!
On their current "capabilities" page they provide different aspect ratios: standard processing: 0.5:1, advanced processing: 0.75:1. They also offer some other microvia techniques, and you need to contact them to get more details.
Very useful video. Thank you, Robert.
I have to add that using micro vias on top of each other is not an issue ( n most cases) but putting micro vias on buried Vias is not a good idea.
Also when using Altium, crossing plane layers with micro vias will result in an error of not having a pad in the plane layers (this is a software issue by Altium). the solution is to using a signal layer instead of a plane layer and filling the layer with a polygon.
Thank you very much Saeed for your feedback. Very useful!
This was is a very helpful video. Thank you.
I would very much like to see a follow-up video about the board stack-up you illustrated, and how to maintain the correct track impedance for signals that use staggered micro-vias on the outer two layers, then a signal layer below that, and only then a (ground) plane layer below that.
If the wave is in the dielectric material between the trace and the ground plane, how do we calculate the requirements with staggered micro-vias layers that each have different distances from the nearest ground plane.
For example, do we need different trace widths on each layer to maintain a consistent impedance.
Thank you very much Nicholas for your feedback. For the designs I have done, I have not been thinking to much about impedance in VIA (there is not really much what I can do about that). The same is about the very short tracks on L2 (not really many options what to do with these). However, if I will have a chance to design a very high speed boards, I will make a video about that.
@@RobertFeranec Thank you
Robert , at end you forget to have tear drop on via , all via should have tear drop , special those Microvia , and suarly all through hole via ,
this is the way I do ,
P.S. Altium can also generate via drill hole file per layer too , for easy manufacturing
You have every information I may need. Great. Thank you!
You can use longer microvia, i.e. from layer 1 to 3, instead of going from 1 to 2, then moving to different place, then 2 to 3. They will be made as 1 to 2, and from 2 to 3, and aspect radios between each layer will be fine. You might want to enlarge the ring size a bit on the layer 2, to ensure the proper registration, but it shouldn't be a problem, especially if the 2 to 3 is the copper filed via. Basically building a taller via in two steps, as a tower. However, you need to check with the manufacturer how to do it.
yes, that is one of the options
very informative thank you Robert
Excellent Video. Thanks.
I am just working via in pad, it’s great helpful.
I am very happy you found it helpful
Hi Robert, many thanks. I will try it.
Hello. I have some interesting board this is NanoPi NEO-LTS
. It's interesting because that board has allwinner h3 chip with 0.65 mm pitch and it's some how routed on 4 layers pcb!!!(you can check out this on theirs web site) I am unsoldered processor and ddr3 memory and discover that they break most of the rules that recommended in design guides, distance between positive and negative trace of differential pair same as distance to other traces and it's about one trace width. But It's actually works fine. And Yes they place vias between pads.
Answered a lot of questions and great tips. Thanks a lot
Outstanding!
Great information as always Robert!
I think you get it reverse in the cost analysis. If you make a big PCB, or big panel, it will cost you relatively less. If you are making a single small board, then it will relatively cost you way more.
I meant if you use the same technology. For example, if you us all the uvias and buried vias etc, then bigger PCB is going to be a very expensive, comparing to a small one. On a small PCB you can use almost any technology and it is almost always going to cost just a couple of dollars for higher quantities.
Thank you for video! it was really useful and interesting.
Thank you very much Roman
@44:40mins I thought you couldn't go from layer 1 to layer 3 because of the fabrication process. They glue boards together and then drill through the stack. So, you could go from layer 1 to layer 2, or layer 1 to layer 4, but not layer 1 to layer 3. Sorry if that is not clear.
Hi Robert, very helpfull video. You shared a lot with me Thank you. You can use Draftsman documentation in Altium for board specification and drill table.
Thank you Wlada
Hi Robert,
I don't agree about via definition at first 10minutes. You have forgotten on plating thickness for through hole via. If we define hole of via in altium of 0.15mm this is the finished plated hole. However the manufacturer have to drill via with 0.2mm bit in order to have of 25um copper on vias wall. Next, we have IPC standard an minimum anular ring. For standard process they require 125um in oder to avoid brake out on ring.
It yields 150um + 2x25um + 2x125um is 450um outer diameter of via.
So it means, we have to know the drill they will use for mnf. process in order to provide reliable plating.
Another question, have you found how define vias in altium which should be plugged according type VII.
For example, we had via and soldering pad both had diameter of .0.6mm. In altium drill file they have been marked with same symbol T4= 0.599mm. Pcb manufacturer pluged at the end everything, both vias and pads. How avoid this ib future?
Br
Josko
amazing one
Hi Robert,
first of all, thanks for this video, congratulations on the 30k subscribers and thanks for your HARDWARE DESIGN TIPS series. I learned so much from them for my first big PCB. Maybe we get another 25 videos in this series now that you have reached 30k subscribers!?!
Regarding the documentation of what vias should be copper or resin filled, you might take a look at draftsmen. With it you can document your board stack including drill/layer pairs and/or backdrilling, ... and you can add textual comments. Whether it is able to highlight those vias which have to be filled, I currently cannot check but I think so.
Draftsmen is a pretty good tool and advanced in the last versions of AD compared to its feature set when it was release with (I believe) AD15. Check it out.
Thanks and please let us participate on your knowledge and experiences in the future. Stay healthy!
Tobias
Thank you very much Tobias. I am very happy that you found the videos helpful. PS: I will have a look at possibilities in Draftsman. I was looking into PCB, as often for PCB manufacturing I place everything into gerbers, so people processing the gerbers see also all the manufacturing notes in one place together with layers.
i love this mil to mm inserts
Informative design for us, Robert. I wonder that how can I put and cover/plated the via in pad as you did in 10:53?
Robert, I have a question. If you do not use uvia stacked (top of each other), but go sequentially stepwise (staggered via) TOP - Layer2(GND) - Layer3(Signal). In this case, the Layer2 will have a short piece of track that will not have a reference layer. I think this is the same as drawing a track over a gap in the reference layer. ? Or not? (43:35 timing)
Awesome upload Robert.
Thank you very much Upcycle Electronics.
Hi Robert Feranec,
Very informative video, I learnt alot about VIA ON PAD, plugging and filling. Thanks alot for your selfless helping effort.
You mentioned in the video, that you change the via size to 0.201mm for copper filled via and highlight in other document that 0.201mm vias are the copper filled ones.
Instead, we can use the description column in the drill table to indicate that 0.201mm vias are copper filled ones ?
Is it possible ?
Regards,
Naveen
Very interesting video. Thank you very much :-)
Best content ❤️
Well done, thank you!. I think you said you felt uncomfortable in using the 0.350mm via as a through-hole via between pads (in a dog-bone configuration), yet it sounded like you were going to use that same via in the middle of the processor pad in a "via in pad" configuration. Why do you feel that the 0.350mm via is too small for the first configuration, but acceptable for the other?
When trying to prototype a hdi board (without via in pad) i found prices are above $1000 for a small board, right?
Yes, that is right. We often pay between $3000 - $5000 USD. But they need to manufacture whole panel, so if your board is small you can get 15 boards for almost the same price as 5 boards.
Thanks Robert!!!
Thank you Simon
Excellent information
Thank you Alisson
Very good Robert!
Thank you very much Carsten
does anyone have a reference design where is shown how to fan out a bga with 0.4mm pitch
Hi, Where can I find the document of Exception PCB?
Thanks a lot Robert, very useful video again ! I wonder that via size can be smaller than BGA pads ? Is there any problem about that. For example: 0.5 mm BGA pad and 0.35 mm via (via has 0.15 mm hole size) on this BGA.
Hi Robert,
How will you take care of CAF in microvias..I mean what should be the distance between two microvia in order to avoid CAF issues
Mmm, if we dont fill microvia with neither copper nor epoxy, and the microvia is small enough, will the tin ball from the bga be sucked through the microvia?, perhaps it won't because of the big viscosity of the molted tin. It could be a cost effective solution.
I have used a 100um microvia hole in a 400um BGA pad without filling and no problems in SMD. There may be a bubble in there but problems have not shown up.
Hi Robert I have a beginner doubt on solder mask expansion. What does it stand for? Does it mean solder resist is not applied in the area of solder mask expansion? That’s what I understood from the last part of the video. That if the expansion makes the sliver too small solder bridges may form between adjacent pads. Am I correct in this understanding?
Exactly. Also just to clarify, the solder mask expansion is the additional area apart from the pad where no solder mask is applied.
Hi Robert. Please can you show the layout of a simple power net, say +5v and gnd, nothing complex, best practise for the symbols and the net names.
i struggle with how to set them up and i always have errors after compiling. I use altium V17. Many thanks in advance. Be safe in these trying times.
I have some of tutorials for older Altium ( welldoneblog.fedevel.com/2012/04/27/6altium-tutorials-for-newbies/ ), but what you can find useful may be actually number of videos I created about designing boards (browse through the search results, maybe you will find something interesting): welldoneblog.fedevel.com/?s=starting
Robert, sometimes I see you put via close to smd pad at Altium. In this case, you change rules ? usually I send boards to JLCPCB and they are some constraints using via close to pads
I do nothing special there
@@RobertFeranec Thanks.
Hi Robert, is there a link for the dfm guidelines on exception pcb website or should we contact the company to obtain the document?
You are not the only one asking, so I attached the file here: designhelp.fedevel.com/forum/test/pcb-layout/15903-via-on-top-of-pad?p=15975#post15975
ty
Thank you gatlingword
very useful information indeed! Thank you Robert.
So, the inforamtion about via-filling that I understood is like this: to have copper-filled through-hole vias, one has to explicitly tell the PCB manufacturer to do that and there is no direct way to specify that in Altium. Is this correct??
Also for larger power devices like MOSFETs, can the vias-in-pad be defined in the footprint library itself?? Or shall one use it only in the PCB?
No, you can't specify it in Altium. Simply use an unique hole dimension for the vias which are going to be filled so you can simply list them and tell the manufacturer that these are the vias you would like to fill. PS: you can define them in library, but do not forget to include these vias in the list of filled vias.
@@RobertFeranec Thank you so much for the response.. so nice of you ...
A lot of information, thank you so much Robert.
I have a question for you. When we should use dog-bone fanout over via in pad or vice versa?
Dogbone fanout is used because it is cheaper?
Canberk
Thanks for the video Robert, very interesting!
I wonder if you know if there is any upper limitation in drillsize when doing copper filled vias for use as thermal vias? BR Tomas
Thank you Tomas. I was thinking exactly the same this morning :) I should also ask the upper limitations. I will need to double check that.
@@RobertFeranec I guess its just a matter of time as larger holes requires thicker copper layer to be added to be fully filled up...?
Are the design files of imx8m rex available?
No, the module files will not be available. Baseboard files will be probably open source.
I wanna Fanout 0.4mm pitch WLCSP package I believe it is impossible to put Vias between pads, did u try something like this before ?
I was also trying to same. Also the reason for me to watch this video to handle the fanout for 0.4 pitch BGA. After watching the video i decided that only possible solution is using via-in-pad with filled or caped vias and PCB needs to be at least 6 layers. Blind(L1-L2) and burried vias (L2-L3) has to be used because of 0.1mm hole size. I also talked to my friends who have experience in PCB assembly. They said it is more complex and more expensive. In my design there was only one component like this. I watched the video to learn how to use via-in-pad. After watching it i decided not to use 0.4mm package and change it to QFN.
@@BurakEnez exactly like what I did
Simplified version of 1.5-hour video: don't do it!!!