Latch-up prevention in CMOS | Various techniques for latch-up prevention | Issues in Physical design

This video explains the various techniques to prevent Latch-up issue in CMOS technology. Guard ring, well tap cell, retrograde doping, epi layer, Silicon on Insulator (SOI) and many more have been explained in details.
Placement of Well tap cells in physical design and how it helps to prevent the latch-up has also been covered in this session.
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VIDEOS IN THIS SERIES
1. Latchup issue:
• Latch-up in CMOS Tech...
2. Latchup prevention techniques
• Latch-up prevention in...
3. Antenna effect:
• Antenna effect in VLSI...
4. Antenna prevention techniques
• Antenna Effect Prevent...
5. Electromigration issue in ASIC
• Electromigration in VL...
6. IR Drop Issue in VLSI
• IR Drop issue in VLSI ...
7. On-Chip variations
• On-Chip Variation in V...
8. Crosstalk effect in VLSI
• Crosstalk issue in VLS...
9. Crosstalk prevention
• Crosstalk issue and p...
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