LATCH UP PREVENTION

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  • Опубликовано: 4 ноя 2024

Комментарии • 21

  • @nikkiscars4222
    @nikkiscars4222 3 года назад +5

    Another way of preventing latch up is P ring around P device and N ring around N device which will act as collector and reduces the BJT collector current and hence the beta

  • @arun65394
    @arun65394 4 года назад +1

    Hello sir,
    You taught very well, it is great insight to learn new prevention techniques... Thank you so much sir...

  • @mrashokkumarkpm
    @mrashokkumarkpm 4 года назад +1

    Very neat explanation sir... Please continue your good work.. waiting for more videos ! 💐

  • @mistakesimake2012
    @mistakesimake2012 4 года назад +2

    You Guys are amazing .. and doing awesome work

  • @rajatmaheshwari186
    @rajatmaheshwari186 3 года назад +2

    Please also make video on FINFET LATCHUP.

  • @vnnmichael
    @vnnmichael 8 месяцев назад +1

    if substrate Resistance is reduced , how is it lowering the chance of forward bias or V(be) ? Please explain

  • @analoglayoutdesign2342
    @analoglayoutdesign2342  4 года назад

    If anyone needs to discuss further, please send me a text on +91 7892400015

  • @shahidafridi90
    @shahidafridi90 4 года назад +1

    well explained Sir !!

  • @lokeshsutar3476
    @lokeshsutar3476 4 года назад

    It was very helpfull...thnk you sr.
    Can we have a lecture on short channel effects in a MOSFET..... please...

  • @211SANDEEP211
    @211SANDEEP211 4 года назад +2

    Thanks

  • @rohanyadala9096
    @rohanyadala9096 Год назад +1

    Super...

  • @lokeshsutar3476
    @lokeshsutar3476 4 года назад

    Thnk u sr...it was very helpfull

  • @ayyappann6860
    @ayyappann6860 4 года назад

    Why big devices has more chances of latchup in drivers?

  • @rajasekharnallamekala4950
    @rajasekharnallamekala4950 4 года назад

    if p sub is not connected to gnd , what will happen and which pblms will rise ?

    • @analoglayoutdesign2342
      @analoglayoutdesign2342  4 года назад +3

      in that case, where should it be connected? We cant leave it floating. Psub should be connected to thle most negative voltage of the design... generally 0v. otherwise there would be substrate diode or body diode forward biasing condition..meaning i connect substrate to 1V and drain of the NMOS to 0.2V, substate to drain pn junction (substrate is P and drain is N) will get fw biased.
      Many unpredictable things will happen... hope this answers

    • @rajasekharnallamekala4950
      @rajasekharnallamekala4950 4 года назад

      @@analoglayoutdesign2342 Wil u upload video on Op-amp and LDO .

    • @analoglayoutdesign2342
      @analoglayoutdesign2342  4 года назад

      yes...but will take little time....

    • @rajasekharnallamekala4950
      @rajasekharnallamekala4950 4 года назад

      @@analoglayoutdesign2342 OK thanks for your response