Truly appreciate your videos that explain the design principles from basics. I have a question related to high speed differential design. Is it a good idea to widen differential trace width to maintain impedance and spacing between the traces when they are diverging to connect to pads or pins? How would it affect the insertion loss and reflections when the differential traces have to diverge without increasing trace width vs. widening trace width?
I have a question about impedances. Most calculators work from the final copper sizes. So, how do you work out or specify the copper thicknesses on the outside of a pcb? As most use 1oz inner copper (these are not plated up), and a 1/2oz outer copper which gets plated with an additional 1/2oz copper to connect down vuas and plated holes.
The copper weight value that is put into the calculator is typically going to give a very close impedance to the true value because the impedance does not strongly depend on the copper weight. It matters more at higher frequencies because of the skin effect, going from 1 oz to 2 oz creates a bigger change at higher frequencies, as well as reducing losses from the skin effect. Also plating thicknesses are not huge compared to the bare copper, so applying plating might be a minor change in the finished copper thickness until you go to very small weight copper (like 1/4 oz).
I don't see why decreasing the self inductance of a trace will increase it's immunity to xtalk, I thought only the mutual inductance matters for inductive xtalk
It's the ratio of mutual inductance to self inductance that matters. Changing that ratio of trace width to GND decreases the self inductance but also decreases the mutual inductance assuming you do not put the traces much closer together by widening them. It's when you start packing the traces closer together on a thinner laminate that you can get a crosstalk penalty and you may need to space them out more (such as change from 1W spacing to 2W). I discuss this and show some simulation results in my PCB West presentation for this year, and I'll be including it in a course coming soon.
If you look at the PCB Trace Inductance blog linked in the description, there is a link to email my company to get a copy of the spreadsheet. You can also message me on linkedin and I'll send it to you.
Not that I know of, maybe it got moved? I know there was some kind of new integration into Altium 365 workspaces, but I do not use the viewer very often so I am not sure what is going on with the viewer website.
Thank you, Dr. Peterson.
Truly appreciate your videos that explain the design principles from basics. I have a question related to high speed differential design. Is it a good idea to widen differential trace width to maintain impedance and spacing between the traces when they are diverging to connect to pads or pins? How would it affect the insertion loss and reflections when the differential traces have to diverge without increasing trace width vs. widening trace width?
Call your FABRICATOR... Sound advice that will save you time and money!
I have a question about impedances. Most calculators work from the final copper sizes. So, how do you work out or specify the copper thicknesses on the outside of a pcb? As most use 1oz inner copper (these are not plated up), and a 1/2oz outer copper which gets plated with an additional 1/2oz copper to connect down vuas and plated holes.
The copper weight value that is put into the calculator is typically going to give a very close impedance to the true value because the impedance does not strongly depend on the copper weight. It matters more at higher frequencies because of the skin effect, going from 1 oz to 2 oz creates a bigger change at higher frequencies, as well as reducing losses from the skin effect. Also plating thicknesses are not huge compared to the bare copper, so applying plating might be a minor change in the finished copper thickness until you go to very small weight copper (like 1/4 oz).
I don't see why decreasing the self inductance of a trace will increase it's immunity to xtalk, I thought only the mutual inductance matters for inductive xtalk
It's the ratio of mutual inductance to self inductance that matters. Changing that ratio of trace width to GND decreases the self inductance but also decreases the mutual inductance assuming you do not put the traces much closer together by widening them. It's when you start packing the traces closer together on a thinner laminate that you can get a crosstalk penalty and you may need to space them out more (such as change from 1W spacing to 2W). I discuss this and show some simulation results in my PCB West presentation for this year, and I'll be including it in a course coming soon.
I cant find the excel file. Where would it be?
If you look at the PCB Trace Inductance blog linked in the description, there is a link to email my company to get a copy of the spreadsheet. You can also message me on linkedin and I'll send it to you.
Is Altium Viewer down for good?
Not that I know of, maybe it got moved? I know there was some kind of new integration into Altium 365 workspaces, but I do not use the viewer very often so I am not sure what is going on with the viewer website.
That thumbnail image screams 'AI-generated'. Just because you can, doesn't mean you should.
You'll have to ask the editorial team at Altium about that!