Remove Ground Below Impedance Matching Networks?
HTML-код
- Опубликовано: 4 авг 2024
- Tech Consultant Zach Peterson explores whether or not you should remove ground below the components in an impedance-matching network. He examines a dev board for the NRF52 to answer when it's appropriate or not to remove ground.
0:00 Intro
0:37 Revisiting the nRF52 Design
2:26 Removing Ground & Reducing Parasitic Capacitance
8:44 When to Remove Ground
For more RF Design videos, click here: • RF Design
For more PCB Design for Intermediate Users videos, click here: • PCB Design for Interme...
For more Tech Consultant Zach Peterson videos, click here: • Technical Consultant Z...
👉 Should You Remove Ground Below Impedance Matching Networks?: resources.altium.com/p/should...
👉 nRF52 Example PCB Design Series: • nRF52 Example PCB Desi...
👉 15 Days Free Altium Designer Access: altium.com/yt/altium-academy
Don't forget to follow us on social to stay up-to-date on the latest Altium Academy content.
👉 Follow Altium on Twitter: / altium
👉 Follow Altium on Linkedin: / altium
👉 Follow Altium on Facebook: / altiumofficial
👉 Ready to try the industry's best-in-class design experience yourself? Download it today and get started! www.altium.com/downloads?utm_...
The Altium Academy is an online experience created to bring modern education to PCB Designers and Engineers all across the world. Here you can access a vast library of free training and educational content covering everything from basic design to advanced principles and step-by-step walkthroughs. Join industry legends as they share their career knowledge, review real-life design projects, or learn how to leverage one of Altium's leading design tools. No matter your level of experience, the Altium Academy can help you become a better Designer and Engineer!
About Altium LLC
Altium LLC (ASX:ALU), a global software company based in San Diego, California, is accelerating the pace of innovation through electronics. From individual inventors to multinational corporations, more PCB designers and engineers choose Altium software to design and realize electronics-based products.
#Altium #PCBdesign #ElectronicsDesign 
Наука
Hi,
I've removed ground before in some projects, but it was for another reason. Prepreg was thin between top and second layer and 50ohm trace width would need to be very small (and manufacturing tolerances in comparison to width very big). In addition, component pads (which would be much bigger than trace) would cause big discontinuities in impedance and cause reflections. Thin trace is having higher DC resistance so ohmic loses would be also higher. In case of removing the GND plane below RF circuit is very important to have enough vias around output to GND so that field does not spread (and impedance does not get higher at that transition from IC to transmission line).
I don't see a reason to avoid 'parasitic capacitance' specifically because if it is in correct ratio with parasitic inductance, then it makes controlled impedance transmission line (of any needed impedance). If you try to avoid capacitance by cutting ground layer, then you also automatically increase inductance of all traces going over that area, so in effect you create higher impedance line, which I think it was not intended in this case. Output impedance of semiconductors is usually lower than 50ohm and if anything first part of the trace should probably have lower impedance than 50ohm (to be matched to output amp impedance).
Am I missing something?
Best regards, Darko
I'm still wondering the same thing. If Z=√(L/C), then reducing C will modify Z. If you keep the ratio constant with right geometry then what's the need for reduction?
The reason I think it's needed is because the component footprints are not the same as the trace size, i.e. if your stack up 2D solver says a 10-mil trace has 50 ohm characteristic impedance, then the 0402 ac-coupling cap should have an antipad/ cutout region under it since the pads are wider than 10 mils.
If you're just talking about the impedance of the traces you are correct, if you remove the ground and resize the trace so that you always hit the target impedance then you are always maintaining the same ratio. That's not the issue, the issue is that the traces/pads have additional capacitance with respect to the components, so the components act as if they have different values because the signal acts along both the components and the connecting pads/traces simultaneously. The additional parasitics modify the center frequency and Q factor of the network, so now the network may not provide the matching you expect at your target frequency.
@@scottpelletier1370 The component pads also need to be considered, they do have different inductance and capacitance than the traces when the widths are different.
That`s a great video and this is a very important discussion. For a dev kit, you'd be willing to make the nominal component values dominate, since you want the customer to use that dev kit to do experimentation and trust the components values, speeding up the design (different antennas). Once the design is done, another way to get rid of that layer-to-layer parasitic is to design the impedance matching network using CPWs. The coplanar parasitic capacitance is going to dominate over the layer-to-layer capacitance, hence making no significant difference removing or not the ground below. As always, great content Zach!
I looked at this issue with a coplanar feedline looking into an SMA connector in a recent video. You can actually see that when the trace (in this case SMA pad) is very large and the dielectric to ground is very thin, you actually do get a big deviation in the impedance on that pad even though the coplanar ground clearance is the same everywhere. It's only once you have the spacing (S) to dielectric thickness (T) ratio to be very small that you get the impedance convergence to be stable, which is exactly the case you mention where now the fringing capacitance from coplanar ground dominates over the layer-to-layer capacitance.
@@Zachariah-Petersonthank you for the follow-up on this. I totally agree. The shortest gap always dominate. In general, I'd not use CPW if the layer-to-layer height is close to the CPW spacing to GND.
If a capacitor value of my calculated impedance matching network is not within the standard value of what is offered, I often will use the nearest lowest available value and use the parasitic capacitance to compensate. That being said, component value tolerance is something to take into consideration as well.
These are both great points
Thanks Zak - I notice you avoided any discussion on the spread of E/H fields due to the removal of copper GND. This can be an important source of crosstalk.
Yes it can and I didn't want to muddy the issue, also in the example design it was set up as a grounded coplanar line specifically because of the field spreading issue. So as long as you have some isolation and not too much routing near the coplanar line it should not be an issue. But for regular microstrip you are right and you might see stronger coupling in that region.
That actually reminds me, we have another video on crosstalk reduction simply through the presence of ground near interconnects, it's coming out soon and addresses the exact point you are making, just not specific to impedance matching networks.
@@Zachariah-Peterson Great I'm looking forward to that!
Vias from TL to BL of shunt matching caps will do more harm than parasitic capacitance. Also: these 'parasitic capacitance' is not 'parasitic' - it is a part of matching network that will just change the matching network components value.
I would consider it parasitic ... it is undesired. Also those vias are necessary, so this becomes an optimization problem: doing the best you can without going overboard.
I only use the word "parasitic" in that it is not desired or expected. You are right it is just the self-capacitance of the pads/traces etc., parasitic is not being used in reference to mutual capacitance/inductance between two traces as would be the case with crosstalk.
Hi Zach, how do you know the Cp is about 3pF/inch? How to determine that value?
Is that a rule of thumb?
The reason I am stating that is because it is assumed in this example that we are dealing with a 50 Ohm microstrip, which would have capacitance of approximately 3 pF/inch on Dk 4 laminate. In this case the parasitic capacitance (Cp) is just the self capacitance of the traces and pads connecting the components in the matching network. It ends up being on the order of pF of total additional capacitance within that matching network; similar results are observed for inductance. The case with the nRF52 layout uses a coplanar line with ground so it is a different value, but you can calculate it. If you are using a standard coplanar waveguide with ground you can view the Cp value in the Impedance tab inside the Layer Stack Manager in Altium Designer.
Zack show us the results with your nRF52 board already. 😅
This could be a bit off topic. But I wonder what difference it makes to have stitching ground vias with thermal reliefs vs without.
Sorry for the late reply, but wanted to address anyways. Yes it all does make a difference, but it's a matter at what frequency you start to notice. For small thermal reliefs, you can analyze this based on a fraction of the relief connection length compared to the signal's wavelength. Because thermal relief connections are just thin short transmission lines, they have some inductance and capacitance, so their effect on propagation can be noticed more at progressively higher frequencies.