Nice video, thank you. Return loss is one of my favorite things to try and improve. Artwork is very important, dont over look it. Sharp corners on gnd planes and signal traces are your enemy. Each one is a point of noise, emr, and impedance degradation. Some quick pointers for improving an RF trace return loss: -Change your trace-to-space as you taper up ot the wide Pad, to the SMA pad. The SMA itself is a "taller" trace when considering the center pin. Also the Pad is wider, so your space to ground should change accordingly. -Remove soldermask under the SMA near the board edge. On your bottom layer have a soldermask cutout and put a nice solder bridge connecting the underside of the SMA to the EVB. This can improve return loss a few dB. -Use flat tab SMAs rather than calendrical. The conversion from flat CPWG or microstrip to a cable can influence return loss. Flat tab SMAs make that transition from trace to cable smoother. -Use some PTH around the SMA gnd area. Having solder connect all GND layers from top/signal though the board usually results in better grounding, thus better return loss. Even better if your sma has a 90deg though hole ground post. Just a few things that come to mind.
Simbeor was used in this demo, and Simbeor actually runs in the background in Altium Designer inside the Layer Stack Manager for impedance calculations. A free option is OpenEMS, which I am still learning and will probably do a demo on it in another video.
Nice video to understanding the matching Impedance but I have question here SMA connector Trace surrounding GND vias with Solder mask open is it require for HF Traces or we can match the Impedance is it fine ? Any specific reason for GND Via's.
Hi Balaji, The solder mask opening on the trace is not required for RF designs, but it is customary to do so because the solder mask is lossy at GHz frequencies. The loss tangent of most LPI solder mask is 0.02 at 1 MHz, compare that to FR4 which has a loss tangent of 0.02 at 1 GHz, so it is much more lossy than the PCB substrate. That is why we like to remove solder mask on microstrip traces for RF signals. The GND vias are used to form a coplanar waveguide that helps confine the electromagnetic field around the trace and thereby provide more shielding to other components. Also not required but this was a specific case where we wanted a coplanar waveguide with ground and it is typical to do this in this particular type of RF design.
Hi Balaji, allow me to add to Zach's answer: - Solder mask: beside high loss of solder stop paint, this paint is rarely defined in its Er. Additionally, the thickness varies from batch to batch. The easiest way is to skip it and you get air as isolator. In cases you need to protect your trace against environment impact, special paint or coating is one way. Another way is to put the track inside the PCB. Both ways have to be used with caution and using simulation/experience. - Surrounding GND vias: Also named as via fence is a good way to confine an RF path, like Zach mentioned. Keep in mind that via's parasitic capacitance may drop your impedance by 1 to 5 Ohms. - A good practice is to add an RF track with connector and termination resistor on your board or even on the surrounding frame. In this way you can check impedance and connector matching.
Hi@@Zachariah-Peterson . Does the solder mask layer add any noticeable loss in practical scenario, since its thickness might be very low as compared to our PCB laminate thickness corresponding to our RF trace🤔? I once did simulation of a trace with solder mask as a dielectric layer defined on top of it (Dk = ~3.2, Df = 0.025, thickness = 35 micron) , and the result was hardly any different than the case without one. But practically does it affect significantly I would like to know..🤔
I doubt this becomes significant within the rated frequency range of the connector, but the pin's diameter affects this impedance as well. I was just wondering if anyone has checked the composite structure with a 3-D field solver?
For that style of connector, the 50 Ohm rating is known to be good beyond 10 GHz, so for this application we're good, the main issue is the footprint. When you get beyond that limit it's a good idea to consider switching to the edge locking style I showed on the example board, or to switch to an all-SMD style that bonds directly to a small circular pad. Those signal launch footprints for SMD coax connectors can be designed to operate at rated impedance out to something like 90 GHz.
@@Zachariah-Peterson Thanks Zach, I suspected as much. It's just that as the wavelength approaches the physical dimensions of the connector one has the think these usually negligible issues can become significant.
Hi Zach, How many layers do you use in this project? Is it 4 layers board? If yes, how many layers do you put the ground cut out? Can I cut the ground in the inner layers and still pour the ground in the last layer?
This was a 4 layer board, thin layers on the outside. I cut the ground on L2 and L3, and I kept the ground on L4. By doing this I was able to show that the pad's characteristic impedance looking into the SMA was very close to 50 Ohms.
Hi Zach, there's one more query from my side. When such wide SMD components pads are used with cutouts in layers below, does that mean that the return current (corresponding to the Pad area) will flow through the chosen ground layer, which is situated now some distance below the original ground layer. If the pad is an CPWG arrangement, it's understandable that return current might take the coplanar ground route for its proximity to the pad. But what if its a microstrip? Now, if the return current do flow entirely through the lowest level ground plane, then I can see a current loop is getting formed, surrounding the volume constituting the open spaces from all the abovementioned layer cutouts (hope I am giving the right picture here to visualise easily). Will such loop and its resultant loop inductance be significant enough to have any negative impact from noise or EMI point of view?
Let’s just assume for the moment that the wide pad with the cutouts has 50 Ohms matched to the input feedline. In this case it has nearly the same capacitance as the thinner trace on thinner layers. I think that as long as the layer does not get too thick the region occupied by the displacement return current scales approximately linearly with the distance to GND. So if you cut the internal layers but keep GND on the bottom layer, the span of the return current in the GND plane scales similarly because the fringing factor Kg in the RLCG model should also scale in the same way. This might not hold all the way up to a 62 mil board, it is something that would have to be checked in an EM field solver. If you have no GND anywhere then you just created a strong radiator!
has always, great video and explanation. I see very often part of the ground plane without silk screen on it, and many times surrounding the edge of the board, mai I ask why? what benefits brings to the design? Best regards.
I think you mean parts of the ground plane without solder mask. On signal lines, this is done to remove the lossy solder mask from the region of the conductor where return currents arise, which will reduce total losses seen by that signal. In the other case, when used on the edge of the board, there are multiple reasons this might be done. One reason is to provide a sink for any ESD pulse, another reason is to provide a connection to a shielded enclosure. With the shielded enclosure connection, the enclosure is not attaching directly to the system ground plane, instead it is attaching to a guard ring around the edge of the board, and this ring connects somewhere back to ground with a low impedance connection.
@@vitorperez3283 I'm putting together material for some advanced courses, you can follow me on linkedin and I will give an announcement when ready. If you want to learn the basics, you can sign up for education.altium.com for free
No you can't apply rules just to footprints. The only way to replicate rules across projects is to export/import design rules between projects or use templates
Hi Zach! Thanks for the video! I would like to share that I have seen or worked with RF boards having such SMA connectors (not edge mount end launch like the one shown, but PCB mount ones which contacts trace head-on, along with through hole ground pins, eg, MMCX connector) where ground cutouts were given to improve impedance mismatch (many a times, it has been me who suggested the same to layout guy as part of RF review comments 😅). The interesting part is, I have also seen boards having connectors pads with cutout provided in all the layers below the trace - essentially resulting in no ground layer beneath at all! Ofcourse, the pad gets its ground from coplanar ground pours. What can be the reason do you think for this?
That's a really good question. I can't generalize to every case but I can say that there are two instances involving removal of ground below RF lines that make sense. 1) When you have an impedance matching network along the line, removing the ground below this will reduce excess capacitance that creates deviation between the intended matching network function and the actual matching network function. This is most applicable as long as you are below WiFi frequencies. See here: ruclips.net/video/rJQ2GXrKjNA/видео.html 2) When you remove the ground below the feedline but keep coplanar ground, it could allow you to use a wider line, which would reduce losses along the feedline. This strategy plus a lower Dk value allows you to widen the line as needed so that you can overcome excessive copper losses. This is most effective near or above WiFi frequencies on low-Df laminates where you start to see copper loss dominate around approximately the 3-10 GHz range.
Nice video, thank you. Return loss is one of my favorite things to try and improve. Artwork is very important, dont over look it. Sharp corners on gnd planes and signal traces are your enemy. Each one is a point of noise, emr, and impedance degradation.
Some quick pointers for improving an RF trace return loss:
-Change your trace-to-space as you taper up ot the wide Pad, to the SMA pad. The SMA itself is a "taller" trace when considering the center pin. Also the Pad is wider, so your space to ground should change accordingly.
-Remove soldermask under the SMA near the board edge. On your bottom layer have a soldermask cutout and put a nice solder bridge connecting the underside of the SMA to the EVB. This can improve return loss a few dB.
-Use flat tab SMAs rather than calendrical. The conversion from flat CPWG or microstrip to a cable can influence return loss. Flat tab SMAs make that transition from trace to cable smoother.
-Use some PTH around the SMA gnd area. Having solder connect all GND layers from top/signal though the board usually results in better grounding, thus better return loss. Even better if your sma has a 90deg though hole ground post.
Just a few things that come to mind.
how do I find a simulation program - Simbeor?
Simbeor was used in this demo, and Simbeor actually runs in the background in Altium Designer inside the Layer Stack Manager for impedance calculations. A free option is OpenEMS, which I am still learning and will probably do a demo on it in another video.
Nice video to understanding the matching Impedance but I have question here SMA connector Trace surrounding GND vias with Solder mask open is it require for HF Traces or we can match the Impedance is it fine ? Any specific reason for GND Via's.
Hi Balaji, The solder mask opening on the trace is not required for RF designs, but it is customary to do so because the solder mask is lossy at GHz frequencies. The loss tangent of most LPI solder mask is 0.02 at 1 MHz, compare that to FR4 which has a loss tangent of 0.02 at 1 GHz, so it is much more lossy than the PCB substrate. That is why we like to remove solder mask on microstrip traces for RF signals. The GND vias are used to form a coplanar waveguide that helps confine the electromagnetic field around the trace and thereby provide more shielding to other components. Also not required but this was a specific case where we wanted a coplanar waveguide with ground and it is typical to do this in this particular type of RF design.
Hi Balaji, allow me to add to Zach's answer:
- Solder mask: beside high loss of solder stop paint, this paint is rarely defined in its Er. Additionally, the thickness varies from batch to batch. The easiest way is to skip it and you get air as isolator.
In cases you need to protect your trace against environment impact, special paint or coating is one way. Another way is to put the track inside the PCB. Both ways have to be used with caution and using simulation/experience.
- Surrounding GND vias: Also named as via fence is a good way to confine an RF path, like Zach mentioned. Keep in mind that via's parasitic capacitance may drop your impedance by 1 to 5 Ohms.
- A good practice is to add an RF track with connector and termination resistor on your board or even on the surrounding frame. In this way you can check impedance and connector matching.
@@GuentherKlenner Thanks' for kind replay, nice explanation about Er related and Impedance related.
Hi@@Zachariah-Peterson . Does the solder mask layer add any noticeable loss in practical scenario, since its thickness might be very low as compared to our PCB laminate thickness corresponding to our RF trace🤔?
I once did simulation of a trace with solder mask as a dielectric layer defined on top of it (Dk = ~3.2, Df = 0.025, thickness = 35 micron) , and the result was hardly any different than the case without one. But practically does it affect significantly I would like to know..🤔
I doubt this becomes significant within the rated frequency range of the connector, but the pin's diameter affects this impedance as well. I was just wondering if anyone has checked the composite structure with a 3-D field solver?
For that style of connector, the 50 Ohm rating is known to be good beyond 10 GHz, so for this application we're good, the main issue is the footprint. When you get beyond that limit it's a good idea to consider switching to the edge locking style I showed on the example board, or to switch to an all-SMD style that bonds directly to a small circular pad. Those signal launch footprints for SMD coax connectors can be designed to operate at rated impedance out to something like 90 GHz.
@@Zachariah-Peterson Thanks Zach, I suspected as much. It's just that as the wavelength approaches the physical dimensions of the connector one has the think these usually negligible issues can become significant.
Hi Zach, How many layers do you use in this project? Is it 4 layers board?
If yes, how many layers do you put the ground cut out?
Can I cut the ground in the inner layers and still pour the ground in the last layer?
This was a 4 layer board, thin layers on the outside. I cut the ground on L2 and L3, and I kept the ground on L4. By doing this I was able to show that the pad's characteristic impedance looking into the SMA was very close to 50 Ohms.
Hi Zach, there's one more query from my side. When such wide SMD components pads are used with cutouts in layers below, does that mean that the return current (corresponding to the Pad area) will flow through the chosen ground layer, which is situated now some distance below the original ground layer. If the pad is an CPWG arrangement, it's understandable that return current might take the coplanar ground route for its proximity to the pad. But what if its a microstrip?
Now, if the return current do flow entirely through the lowest level ground plane, then I can see a current loop is getting formed, surrounding the volume constituting the open spaces from all the abovementioned layer cutouts (hope I am giving the right picture here to visualise easily). Will such loop and its resultant loop inductance be significant enough to have any negative impact from noise or EMI point of view?
Let’s just assume for the moment that the wide pad with the cutouts has 50 Ohms matched to the input feedline. In this case it has nearly the same capacitance as the thinner trace on thinner layers. I think that as long as the layer does not get too thick the region occupied by the displacement return current scales approximately linearly with the distance to GND. So if you cut the internal layers but keep GND on the bottom layer, the span of the return current in the GND plane scales similarly because the fringing factor Kg in the RLCG model should also scale in the same way. This might not hold all the way up to a 62 mil board, it is something that would have to be checked in an EM field solver. If you have no GND anywhere then you just created a strong radiator!
excelent video, information thank you a lot
has always, great video and explanation.
I see very often part of the ground plane without silk screen on it, and many times surrounding the edge of the board, mai I ask why? what benefits brings to the design?
Best regards.
I think you mean parts of the ground plane without solder mask. On signal lines, this is done to remove the lossy solder mask from the region of the conductor where return currents arise, which will reduce total losses seen by that signal. In the other case, when used on the edge of the board, there are multiple reasons this might be done. One reason is to provide a sink for any ESD pulse, another reason is to provide a connection to a shielded enclosure. With the shielded enclosure connection, the enclosure is not attaching directly to the system ground plane, instead it is attaching to a guard ring around the edge of the board, and this ring connects somewhere back to ground with a low impedance connection.
@@Zachariah-Peterson many thanks for your explanation.
May I ask where we can have courses of pcb design that you advise?
Best regards.
@@vitorperez3283 I'm putting together material for some advanced courses, you can follow me on linkedin and I will give an announcement when ready. If you want to learn the basics, you can sign up for education.altium.com for free
Hi zach .. Can I add rules to footprint in the library itself to be added automatically every time I use it ???
No you can't apply rules just to footprints. The only way to replicate rules across projects is to export/import design rules between projects or use templates
Hi Zach! Thanks for the video! I would like to share that I have seen or worked with RF boards having such SMA connectors (not edge mount end launch like the one shown, but PCB mount ones which contacts trace head-on, along with through hole ground pins, eg, MMCX connector) where ground cutouts were given to improve impedance mismatch (many a times, it has been me who suggested the same to layout guy as part of RF review comments 😅).
The interesting part is, I have also seen boards having connectors pads with cutout provided in all the layers below the trace - essentially resulting in no ground layer beneath at all! Ofcourse, the pad gets its ground from coplanar ground pours. What can be the reason do you think for this?
That's a really good question. I can't generalize to every case but I can say that there are two instances involving removal of ground below RF lines that make sense. 1) When you have an impedance matching network along the line, removing the ground below this will reduce excess capacitance that creates deviation between the intended matching network function and the actual matching network function. This is most applicable as long as you are below WiFi frequencies. See here: ruclips.net/video/rJQ2GXrKjNA/видео.html
2) When you remove the ground below the feedline but keep coplanar ground, it could allow you to use a wider line, which would reduce losses along the feedline. This strategy plus a lower Dk value allows you to widen the line as needed so that you can overcome excessive copper losses. This is most effective near or above WiFi frequencies on low-Df laminates where you start to see copper loss dominate around approximately the 3-10 GHz range.
I love that Zach always mentions to call your fabricator - hmmm I can't see my fabricator engaging in a conversation about SMA connector styles.🙄
I tried with pcbway talking about stackup,they told me first design your board,pay then we'll talk
Non sense!
@@enginstud8852 Haha yes I was thinking about PCBWay when I made my post.
@@chromatec-video Haha, the problem is their sales representatives who don't know much about electronic design
At the end We have to match impedance not only for the traces for the pads too. Because it is traveling for some extent.