NAND Gate as Universal Gate (Part 1)

Digital Electronics: NAND Gate as Universal Gate (Part 1)
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[@shubhamsinha162]

We all appreciate that how easy it looks and how easy it is to understand from these lectures.
But may be we can imagine how hard work it requires to make these type of lectures, how hard work they are doing.
Thanks to you Neso.
We all are blessed with your knowledge and your work

[@emresagr8593]

For second question;
A'+B=(A.B')'
Take a directly, take b'compliment with one nand gate and take two of them with one nand gate it will give us this equation.

[@syra9806]

Thank you!

[@ganeshmula4508]

H. W problems answers
1)3 NAND gates required to implement A'.B
2)2 NAND gates required to implement A' + B

[@yashthakur5712]

you are right brother

[@color_314]

Keep going I like your work and the most important part is you teach better than our collage teacher

[@starkendeavours7072]

H.W questions
1. Minimum 3 NAND Gates required ( out of which 2 Shorted and 1 Normal)
2. Minimum 2 NAND Gates required (out of which 1 shorted and 1 Normal)

[@alishahocane6490]

I got the same answer.

[@Yes-bp1vw]

amazing video, very well explained. a true teacher you are. Thank you sir.

[@kshitijadeshmukh2286]

I typically refrain from commenting but your lecture compelled me for the same .Thank you so much Sir,Very well explained....It's really helpful 🙏

[@abhishekpamadi4782]

Sir pls upload the video of Logic families (RTL,TTL,DTL)

[@thestrappingentrepreneur2822]

Dude your homework. Made me. A subscriber awesome to provide practice problems to viewers

[@jayxcoder]

1) 1 two input NAND Gate and 2 single input NAND Gate (Total 3 NAND Gates)
2) 1 two input NAND Gate and 1 single input NAND Gate (Total 2 NAND Gates)

[@shadabahmed4547]

proper explanation as expected from you ,,,i'm impressed

[@George4943]

What is the resting state of each powered but disconnected NAND? Truth.
The very definition of 'truth' in a strange hardware way.
I started teaching computer science around 1976 and remember when I first taught that NAND was sufficient. I never realized until this very video that NOR is also sufficient. Amazing. Still learning at 80.

[@kavitajoshi4328]

1. 3
2. 2

[@billabong99is]

how the fuck?

[@vasubhatt6160]

@@billabong99is 1)NAND For X only 2)NAND for ~X and Y 3)NAND ~X , Y , Z ,

[@manishkumartailor9389]

Simple and easy to understand. Thanks a lot. Appreciate your efforts.

[@eutopiarhythms8743]

I Love Neso Academy ❤️

[@billabong99is]

so for first one it's A as a double input for a nand inverter and a b input these two are the inputs to another nand you will get A''(double complement)B' then this is a input for a inverter nand and you will get A'B and second one you have A as a input1 and B followed by a nand invertor wich means B' as input 2 for a nand and you get (AB')' using de morgan rule this means A'+B. if i'm wrong correct me . for first one i used 3 nand 2 and for second 2 nand 2

[@pinksky3931]

Thanks a lot for this explanation

[@prathamgoel3386]

Excellent brother

[@MANU-hp2vz]

I was struggling with the second problem. Thanks a lot

[@ajiteshkumar5841]

I got the answer but still have a confusion , what does the term " two " in the question " Find minimum number of two input NAND gates required to implement Y = A'.B " , tells us ? Can anyone describe to me

[@soumiksen7445]

@@ajiteshkumar5841 means NAND gate you will be using can only take 2 inputs . Seeing the question you can make out it can take only 2 inputs A and B .

[@btshatersneedhighfiveonface]

From India 🇮🇳
Thank you 💜♥️

[@naveedkhokhar8711]

1.3
2.2
Love the way to tech....keep it up 😊

[@nittecesectiona1534]

The site for the solutions for home work problems is not opening...especially for this lecture's solutions if I open the site,it is showing error 404...please check it out sir..

[@myonlynick]

i have seen this complaint by many other users in many of his videos. For some reason he does not fix it.

[@interestingandinformationcombo]

I'll be very thankful to you

[@dhanurdharbisoyi2610]

You made it easy sir😊😊👍👍

[@n.p.9997]

Answers for Home Work problems:
1: 3 NAND gates,
2: 2 NAND gates.

[@Mariausman786]

your teaching method is easy to understand for me

[@barsilgen120]

Thanks a lot

[@snehashishbanerjee2575]

🔴H/W problem 1:
✔️ans: 3 two input NAND Gates are required to implement Y = A'.B
.................................................................
🔴H/W problem 2:
✔️ans: 2 two input NAND Gates are required to implement G = A' + B

[@itsall-in-one256]

Hlw sir...there is showing 404 error
We couldn't find the page for homework solutions
Kindly check that sir where is the problem so that we can check our answers.

[@priyontonisaha6845]

Thank you so much sir

[@shivakrishna7970]

watch this at 2x speed to save time.

[@pantelisdj1]

thanks for the tip

[@maybe9357]

Thanks
I usually use this trick on audio books

[@niresh8019]

True👍🏼.

[@eutopiarhythms8743]

I thought only I did that!

[@playergame6398]

Yes from the first video
At 2x its more comprehensive for us

[@patrickjoel8779]

Clear explanation

[@KartikSharma-mt5nm]

Hw questions
1: #3 NAND gates required.
A' >> 1 NAND gate
A'.B >> 2 NAND gate
2: #2 NAND gate required.
(A.B')' = A' + B
B' required 1 nand gate
(A.B')' required 1 nand gate

[@harshitraj8409]

Homework Problem's Solution
1. A'.B = 3 NAND Gates
2. A'+B = 2 NAND Gates

[@saritaverma3890]

Great explanation.

[@usama57926]

thank u brother

[@harcharansingh1997]

1 question 3 nand gate
2 question 2 nand gate

[@abdulroufsiddhu9750]

For question 1 ( 3 NAND ) gates are required
For question 2 ( 2 NAND ) gates are required

[@reydeepu6725]

Can u explain in detail

[@brianmbugua8933]

Please explain

[@aatmakumar4631]

Nice class sir

[@shanmugapriya7554]

Q1.1 two i/p NAND gate(2 one i/p NAND)
Q2. 1 two i/p NAND gate.

[@l.m4631]

thank you

[@marifnishorgo1570]

very helpful

[@tanvipirramba782]

sir plz can u add some more videos on logic families...we need it badly...

[@nitishkumarprajapati6096]

Thanks Sir😃😃

[@superdahoho]

@4:44, are you splitting 1 input into 2 thus inputting it twice into the nand gate?

[@lamiaeid220]

شكرا

[@ajj7794]

all these ppl showing answers and no working :(
Q2 is easy as such i will show working for Q1.
((A Nand A) Nand B) = (A' X B)' = A+B' as such (A+B') Nand (A+B') = (A+B')' = A'XB
3 Nand Gates

[@fanindrakumar835]

Thanx sir ji

[@sameerthor11]

3 nand gates for the first one and two nand gates for the second one

[@geraldnjuguna2087]

nice

[@miltonchowdhury4016]

How can I solve this both of questions.......... Q1. Design and draw a circuit with only NAND gates that performs the action of the following gates (also draw truth tables to confirm the performance).
1. AND
2. OR
3. NOT
Q2. Design and draw a circuit with only NOR gates that performs the action of the following gates (also draw truth tables to confirm the performance).
1. AND
2. OR
3. NOT

[@vijetasarswat9610]

Thanks sir

[@biyyalaharshavardhan7805]

1)3 NAND gates
2)2 NAND gates

[@artwellnjanji]

you are cool man

[@gopikrishnamoodu6152]

1. 3 NAND gates
2. 2 NAND gates

[@chenath9582]

race penguin music at intro nostalgia

[@theriverofrhythm3346]

Answer of Homework problem:
(i) 3NAND Gates --- First to NOT A and second to NAND A and B and third to NOT the result of second NAND gate.
(A' NAND B)' = ((A'B)')' = A'B
(ii) 2NAND Gates --- One to NOT B and other to NAND A and B.
A NAND B' = (AB')' = A'+(B')' = A'+B

[@SchoolGhors]

অর্থবহ। ভালো লাগলো।

[@AlokKumar-zn6ny]

First one is 3 NAND gate
Second one is 2 NAND gate.

[@continnum_radhe-radhe]

🔥🔥🔥

[@theunknown43]

Answers to H.w qns
(1). 3
(2). 2

[@sachinkumarsingh9486]

it's good to be back... hell

[@kaustuvregmi1469]

In NAND as AND, there is a concept of A•A= A isn't it?

[@mariospapadopoulos8706]

Yes that'a law of Boolean Algebra.

[@anshuleshpandey9042]

why we Can't make AND,OR gate using XOR and XNOR gates, what is the reason?

[@mayankchandel4678]

lol i am too late to answer but, maybe cuz XOR and XNOR gates already consists of 4 variables and hence many gates are already involved. While NAND and NOR gates are simpler cases.

[@mitrraaswin4933]

@@mayankchandel4678 lol😂🤣🤣
He must have finished his graduation

[@mdaaweshpatanwala8542]

thanks bhai
hamari mam ko kuch nahi aata hai
bhai tu bhagwan hai
bhai tuhich !!!

[@araghnibanerjee8510]

3:09 mins how are you using both the i/p as two A's instead of an A and a B for the implementation as a NOT gate?

[@vaibhavagarwal3757]

because input in not gate is also one.

[@PriyankaKumari-di8mb]

i) 3
ii) 2

[@chrisatronx]

Wait, so everything is just logic gates? using and or and not? Woah

[@abhishekdas6229]

Sir, you made a mistake at around the 6 min mark. A(complement).B(complement)=(A+B)(complement) and not A(complement)+B(complement)

[@alphasatari]

Abhishek Das that’s the property of NAND gate you give input A’ and B’
To get output (A’.B’)’ it is equal to A+B using DeMorgans law

[@shrinivasgoudannavar1736]

Part 2

[@Shoron09]

3,2

[@vinodeslavath2098]

1)3
2)2

[@deepeshjha8412]

Answers for Homework Problems
1. 3
2. 2

[@yogeshsherawat]

A) 3
B) 2

[@jyotipundir356]

1. 3 NAND GATE
2. 2 NAND GATE

[@dalitso9317]

how are people getting 2 NAND gates for the second question, I'm getting 4.

[@allanraju1570]

Tu tera basics me focus kar, A'+B = (A.B')' ye use kar aur bana

[@satbeersingh4273]

as in question we have to make OR gate whose one input is the complement of A . so first of all we have to make a OR gate from NAND gate which requires two NOT gate at the inputs of NAND gate ,secondly we have to give a complemented A input which further requires one additional NOT gate in the first input but the two NOT gate act as buffer so we can remove them from our circuit and we can directly apply our first input to the NAND gate and the second input is applied through a NOT gate which gives us the required functionality.

[@mohd.husain2224]

Yes

[@roshanrajkumar7827]

Caz ur creepy

[@muhammadyoussef2787]

Homework pages dont work

[@M_ahi]

Legends are watching after 6yrs

[@princebargujar63]

3 for 1st one and 2 for 2nd.

[@tanmay6403]

how ?

[@syedismail1849]

❤️❤️❤️

[@nano7055]

3:42 4:57 7:24 8:38

[@abhinavclass-bc9mn]

breaking bad like intro

[@radwaahmed3808]

bro why do you use Y not X

[@mukeshkumarkunt4389]

1,3
2,2

[@suhrabsharifi8913]

So complex

[@Zappango]

Watch @ 1.5× speed.

[@saikrishna6476]

hello sir

[@ritikshrivastava9442]

(i) 3
(ii) 2

[@GncnrProduct]

1, 3

[@keidoria7359]

i still don't understand

[@vishakhajadhav3577]

For Y=A'.B ans 3
For Y=A'+B ans 2

[@raghuveerdani4046]

You missed out on NAND using NAND gate.

[@haardpatel6803]

1.2

[@akashdas3561]

NAND AS NOR is not understand sir please solve it

[@boiii9793]

my question is that if NOT gate is used to make the NAND gate than how is the NAND gate universal ?

[@Mr7madness]

The NAND gate looks different because it only has one input and it's splitting into two inputs A.A, so it looks like a rectangle/square attached to NAND gate.

[@satbeersingh4273]

definition of universal gate says that every digital circuit can be realized using NAND gate there is no comments about the internal circuit of NAND gate.

[@ogcontent3]

1. 3
2.3

[@natural_beauty573]

3
2

[@universalknowledge7304]

1)2////////2)3

[@tvshowbest6442]

✌️

[@alitoto5452]

bro add some english translation i cant understand anything

[@AjayKrews]

Bicu

[@mounikatallapalli2654]

Video is not clear

[@shadirahman5827]

2
3

[@studentcommenter5858]

How is the first one 2? The answer to the second one is however 2.

[@billabong99is]

i got 2 as a response too