Writing SV UVM Testbench 01 - Design and Specification

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  • Опубликовано: 5 сен 2024

Комментарии • 26

  • @zahraabbaszadeh188
    @zahraabbaszadeh188 21 день назад

    Awesome! I wish I had found it earlier!

    • @openlogic925
      @openlogic925  19 дней назад

      Glad you find it helpful. It is still a long way before I can finish this series.

  • @shriyashgadve
    @shriyashgadve 6 дней назад

    Interesting Video. I find it very helpful. I was wondering if you could do a video on black box verification. It's a fascinating topic and I'm curious to learn more about the how professional go about it and challenges in it.
    Thanks for your great work!"

    • @openlogic925
      @openlogic925  5 дней назад

      Thanks for the comment and the duggestion. I have plans for this series but I'm currently busy with my day job. It'll be awhile before I can create such content. Thanks again.

  • @swetagupta6673
    @swetagupta6673 Год назад +1

    Excellent explanation. Eagerly waiting for the remaining videos of this series

    • @openlogic925
      @openlogic925  Год назад +1

      Thanks for the comment. I'll do my best 😊

  • @suganthiv3577
    @suganthiv3577 Год назад +1

    I am a fan of your videos. Thanks for the great work.

  • @gurun8085
    @gurun8085 Год назад

    Great Content! Will be Waiting to see More videos. Appreciate the Passion towards learning, sharing and the efforts in presenting!.
    I Agree "So many oracles, so few Neos"

    • @openlogic925
      @openlogic925  Год назад

      Could it be... Guru is an alias for "The Architect" 😂. Thanks for the kind comment and the encouragement 😊.

    • @gurun8085
      @gurun8085 Год назад

      @@openlogic925 Thanks for the reply and good words

  • @emilehajj3883
    @emilehajj3883 Год назад

    Great Content! Waiting for the rest of the series

  • @KhanhAn-dv1xr
    @KhanhAn-dv1xr 2 месяца назад

    I am impressed how you explain the theory so understandable, thanks for your contribution. Can I ask about name of the tool you used in 6:23 to plot the waveform?

    • @openlogic925
      @openlogic925  2 месяца назад

      Thanks. I'm just using PowerPoint in this presentation.

  • @filippogiovagnoli10
    @filippogiovagnoli10 Год назад

    Keep going! We need the next part :)

    • @openlogic925
      @openlogic925  Год назад +1

      Thanks. Sorry I've been busy with my job. Sorry bout that. I'll do my best to upload new materials

  • @Zanzara0403
    @Zanzara0403 9 месяцев назад

    Thank you for sharing. I'm interested in the tool you used to create the waveform chart at 4:40. Could you provide more information about it?

    • @openlogic925
      @openlogic925  9 месяцев назад +1

      In this video, it's just power point. I'm not using any special tool.

    • @Zanzara0403
      @Zanzara0403 9 месяцев назад

      ​@@openlogic925 Excellant!

  • @ramchandra9031
    @ramchandra9031 Год назад

    Please do videos on UVM as like Sysyem verilog

    • @openlogic925
      @openlogic925  11 месяцев назад

      The video / playlist you're looking at is for UVM purpose. It'll take time to create the contents.

  • @swetagupta6673
    @swetagupta6673 Год назад

    Sir do you provide any online Training courses on System Verilog and UVM?

    • @openlogic925
      @openlogic925  Год назад

      You mean live session? No I don't do that (I did some live in-person trainings in the past though) . I'm currently busy with a day job. Sorry bout that.

    • @swetagupta6673
      @swetagupta6673 Год назад

      @@openlogic925 Okay I understand. But If there is any plan to start live sessions again,please do let us know.