I like the way you share your knowledge to us. I know this kind of vedio could not attract so much people. So I start to watch every your vedios. Keep Going, Bro !
Hi Mango, thank you for the good question. Cadense virtuoso is more poplular since that's compatible with other layout, post-extracted simulation, IR-EM backend design/verifications and other system IBIS-AMI.
how should I start learning, 1) serdes circuits from basics. & 2) TX(data patha nd clock path),RX (ctle, dfe )circuits from the base level. where to start? Are there any courses?
Hi Sandeep, Nice to meet you. Thanks for the excellent questions. You can start learning the SerDes from the book "Design of Integrated Circuits for Optical Communications" by Behzad Razavi. Then keep asking questions would help you understand every SerDes circuits blocks (in the TX or RX data paths & clock paths) further. Please be advised that the SerDes is a complicated system and may take more time to get the detail easily. If you need any help, please let me know and I could make the video to clarify your questions.
Hi, thank you for sharing the interesting knowledage, I really appreciated it. And there are some doubts I want to confirm to you 1. If we use SerDes, it can cancel the delay problem in parallel transmission, right? 2. If we use SerDes, we need to use the emedded clock, it also needs a CDR, right? 3. So far, if we want to increase the speed of transmission or if there is a high speed signal, it's better for using SerDes, right? Thank you for your patience.
Thanks for the feedback. I put comments below. 1. If we use SerDes, it can cancel the delay problem in parallel transmission, right? [CC] Can you elaborate on this? The SerDes could have more latency than the parallel link. 2. If we use SerDes, we need to use the emedded clock, it also needs a CDR, right? [CC] This is the case, but you still can send the clock; therefore, it's not a must. In the UCIe, we sent the clock :) 3. So far, if we want to increase the speed of transmission or if there is a high speed signal, it's better for using SerDes, right? [CC] That's correct in terms of PPA benchmarking.
@@circuitimage Thanks for the feedback, sorry for the unclear explanation 1. Parallel transmission means several bits can be transmitted at the same time, but there is problem which exists in parallel transmission, need to wait for every bits at the same starting point. However, SerDes doesn't need to wait for other bits, just need to transmit the bit one on one, so SerDes can cancel the delay, is it correct.
@@許育瑛-n5t Thanks for the clarification. Technically, that's correct. But, that's for 1 lane SerDes. If you have multi-lanes (4 or 8) SerDes, you may still need the lane alignments, which would have a delay as well. The good thing is that the delay is shorter since the data rate is much higher in the SerDes than the one in the low bit rate but with great amounts of parallel links.
serdes makes the media small, so even though the throughput is still the same and serdes requires more development time, people are still willing to go with serdes.
The main challenge in converting parallel data to serial is the increase the requirement of bandwidth as each bit duration in serail data gets scaled by the number of data streams getting serailized
Thank you very much for your sharing. It's awesome for my knowledge improvement.
Glad it was helpful!
Good content it helps understanding the concepts more clearly, great job thanks for sharing your knowledge with us
Thanks for the feedback and I'm glad it was helpful!
I like the way you share your knowledge to us. I know this kind of vedio could not attract so much people. So I start to watch every your vedios. Keep Going, Bro !
Hi 大條, nice to meet you. Thank you for your feedback and I'm glad you like it. :)😀
excellent video..very helpful.explained things in a simple way
Glad it was helpful!
Interesting image, comparision between parallel and serial data transmission with bulky wires :)
I'm glad you like it :)
Great stuff !
Glad you enjoyed it
嗨！doctor您好，請問一般在業界設計serdes時，都是使用keysight ads還是cadense virtuoso居多呢？
他們各自的優缺點又在哪裡呢？感謝doctor!!
Hi Mango, thank you for the good question. Cadense virtuoso is more poplular since that's compatible with other layout, post-extracted simulation, IR-EM backend design/verifications and other system IBIS-AMI.
@@circuitimage thx for the reply!! Your video is very beneficial for me!!
@@MangoLin Hi Mango, thank you for the feedback. I'm really happy my video is very beneficial to you. :)
how should I start learning, 1) serdes circuits from basics. & 2) TX(data patha nd clock path),RX (ctle, dfe )circuits from the base level. where to start? Are there any courses?
Hi Sandeep, Nice to meet you. Thanks for the excellent questions. You can start learning the SerDes from the book "Design of Integrated Circuits for Optical Communications" by Behzad Razavi. Then keep asking questions would help you understand every SerDes circuits blocks (in the TX or RX data paths & clock paths) further. Please be advised that the SerDes is a complicated system and may take more time to get the detail easily. If you need any help, please let me know and I could make the video to clarify your questions.
Okay
Hi, thank you for sharing the interesting knowledage, I really appreciated it. And there are some doubts I want to confirm to you
1. If we use SerDes, it can cancel the delay problem in parallel transmission, right?
2. If we use SerDes, we need to use the emedded clock, it also needs a CDR, right?
3. So far, if we want to increase the speed of transmission or if there is a high speed signal, it's better for using SerDes, right?
Thank you for your patience.
Thanks for the feedback. I put comments below.
1. If we use SerDes, it can cancel the delay problem in parallel transmission, right? [CC] Can you elaborate on this? The SerDes could have more latency than the parallel link.
2. If we use SerDes, we need to use the emedded clock, it also needs a CDR, right? [CC] This is the case, but you still can send the clock; therefore, it's not a must. In the UCIe, we sent the clock :)
3. So far, if we want to increase the speed of transmission or if there is a high speed signal, it's better for using SerDes, right? [CC] That's correct in terms of PPA benchmarking.
@@circuitimage Thanks for the feedback, sorry for the unclear explanation
1. Parallel transmission means several bits can be transmitted at the same time, but there is problem which exists in parallel transmission, need to wait for every bits at the same starting point. However, SerDes doesn't need to wait for other bits, just need to transmit the bit one on one, so SerDes can cancel the delay, is it correct.
@@許育瑛-n5t Thanks for the clarification. Technically, that's correct. But, that's for 1 lane SerDes. If you have multi-lanes (4 or 8) SerDes, you may still need the lane alignments, which would have a delay as well. The good thing is that the delay is shorter since the data rate is much higher in the SerDes than the one in the low bit rate but with great amounts of parallel links.
@@circuitimage Thank you for explaining in details, I've learned a lot from you, thanks again.
@@許育瑛-n5t You're very welcome.
serdes makes the media small, so even though the throughput is still the same and serdes requires more development time, people are still willing to go with serdes.
Hi Sai, nice to meet you again. Thanks for the feedback. Those motivations make SerDes development in high demand.
The main challenge in converting parallel data to serial is the increase the requirement of bandwidth as each bit duration in serail data gets scaled by the number of data streams getting serailized
That's correct!
Sir, how can I contact you. I have some doubts. Please reply
Send me an email if you'd like
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@@circuitimage 谦虚了，是你帮助了大家。 不过我想说这个英语，我听得懂😂😂😂
@@vvxx2287 感谢您的反馈。我会尽力提高我的英语发音的清晰度。😂😂😂