SPI Master with Chip-Select, VHDL Testbench

Here I simulate and test the code we added in the previous video. Previously we introduced the Chip-Select in VHDL and now we need to test it.
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[@electromatic2014]

Amazing channel, I really apreciate that you are showing how to work with the FPGAs rather than sticking with Just theory. It is amazing to see how you desing your IP so we can all learn about good practices on using VHDL/VERILOG and start getting used to processes and the rest of the tools. Ill definatly be one more of your patrons from today. Thanks!

[@Ishfarzzz94]

thanks for these videos. they are quite helpful. Quick question. A bit confused about w_Master_RX_Count. I know it connects to o_RX_COUNT. Ran the simulation in Vivado and checked that. it only goes to 1 after receiving c1 and then goes back to zero. what exactly is that telling us?

[@Nandland]

The width of this counter depends on the number of bytes to send. If you're only sending 2 bytes per transaction, the possible values of the counter are 0 and 1. If you send more bytes it will have more values.

[@Ishfarzzz94]

@@Nandland thanks for the reply. Figured it out eventually