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Your Appreciations, care and share matters a lot to me. #EnginneringLove. Let me give the details of few exiting features of Engineering Funda: 1. All the subjects playlist of Engineering Funda is available in comment section. 2. Detailed Syllabus of subject along with chapters is given description of videos.
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Sir, if we change values of both Q & Q' at 4:13 instead of assuming that they are retained, we still get a valid output, or what I mean is we can still justify those values with S=1 and R=1. How is that possible?
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Your Appreciations, care and share matters a lot to me. #EnginneringLove. All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏
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Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your positive comments motivates me, my goal is to create largest community of engineers in entire globe, so please help me for that by sharing this lecture series(playlist) with your friends in social media (watsapp, telegram etc). Thanks and welcome 🙏
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
This cicruit is not a latch it is called a memory element the first condition for having a latch is to have an enable input and it does not satisfy the first condition . Also if anyone have a simulation tool they can check the circuit of flip flops we study online does not work correctly they even change their state when we give a constant value to a clock. So the flip flops circuit we study are not the correct ones. We should always use Master slave configuration for making a flip flop from a latch and the circuit we study are not flip flop they are latches and only SR and D latch exist other flip flop circuit we study does not work at all. So plz provide correct information to the students and keep up the good work.
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your Appreciations, care and share matters a lot to me. #EnginneringLove. All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏
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Sir here we don't write reset first then set second? Like nor latch ? ... Because you said first reset then set but you changed here as first set then reset...
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All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏
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What happens when we change both R and S? If those states:S=0 R=1 and S=1 R=0; acting like memory; then if we change both S and R at the same time ; q and q complement should not be change.Otherwise it is not memory.
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i watched a lot of videos on youtube but i only understood the topic through this particular video. sir, thank you; you saved my life.
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Systematic playlist ❤️🔥🔥
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Thank you sir ...your explanation is amazing I have some doubt in this topic but now...seen your video all doubt are clear ❤❤❤😊
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Thanks!
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absolute gold level content
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Awesome explanation!
Your welcome dear🙏
WONDERFUL EXPLANATION SIR
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Wow beautifully explained
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Yes
Sir, if we change values of both Q & Q' at 4:13 instead of assuming that they are retained, we still get a valid output, or what I mean is we can still justify those values with S=1 and R=1. How is that possible?
Thank you sir 🙌
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6:51 sir at this time we find at s=0 r=0 because we find at 1,1 state that is memory.
This sir Desreves a like
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Thank you for easy explanation
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@@EngineeringFunda sure, you are doing great.
It's clear my concept
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Thank u sir Now i have clarified..
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Wonderful explanation sir
Thank you
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Very good explanation sir
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This cicruit is not a latch it is called a memory element the first condition for having a latch is to have an enable input and it does not satisfy the first condition . Also if anyone have a simulation tool they can check the circuit of flip flops we study online does not work correctly they even change their state when we give a constant value to a clock. So the flip flops circuit we study are not the correct ones. We should always use Master slave configuration for making a flip flop from a latch and the circuit we study are not flip flop they are latches and only SR and D latch exist other flip flop circuit we study does not work at all. So plz provide correct information to the students and keep up the good work.
thank you very much sir
Most welcome
It means that when ever we take S as 1 and R as 1 we have to keep in mind previous case op
Thank uhhhhh so much sir 🙏
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Thank you 😊
thank you very much sir
i have no words to tell you🙏
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thanks a lot
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@@EngineeringFunda your 12 mins video explains a lot better than my 45 mins lecture ☺️
when R=1; Q should be 0 because it is reset state , but here it is not , i am confused
Thanks
Welcome
3:03 why the output of Q' goes to the upper gate,
As the upper state haven't completed first iteration.
Sir here we don't write reset first then set second? Like nor latch ? ... Because you said first reset then set but you changed here as first set then reset...
That is how it is available dear
Thanku sir
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Why s is 1 and r is 1 in this case?
Sir you did it somewt with in 10 mins what my professor couldn't do in 55 mins
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Why are the outputs presupposed to be different?
👏
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Tq sir 💜🫂✨
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@@EngineeringFunda I really appreciate your dedication towards teaching sir keep going, ur helping lots of students to learn 🫂💜✨sir
What happens when we change both R and S? If those states:S=0 R=1 and S=1 R=0; acting like memory; then if we change both S and R at the same time ; q and q complement should not be change.Otherwise it is not memory.
sir aapne using NOR gate likh diya sab mai confusion hori hai pls correct
Done and thanks 😊 🙏
@@EngineeringFunda You are welcome sir 🤗
☕☕☕
Exaplain level and edge triggred jk flip flop as soon as possible
S=1 and r= 1 is prohibited case
I am hot
Thank you ❤
You're welcome 😊