Excellent explanation. I hadn't even thought of putting the current mirrors on both rails, but I bet that helps with keeping the output levels valid for buffers. Have you looked at startup instability? E.g. with 5 or more stages it's possible to have multiple edges in the system - eventually one will dominate, but until it does the frequency can be faster than expected.
Hello! I have a question. In type 1 XOR PLL there is 90 degree phase shit between input and output. And when the two signals are at 90, the average output voltage will be half Vdd. I completely get that part. But my confusion is more fundamental here. Why does the locking occur at exactly half the voltage(Vdd/2)? Any constant phase difference means same frequency. But it locks with 90 degrees difference. Why it locks at VCO's center freq?
Hi, pll is composed by a phase detector and a low pass filter which detect the different phase of two input signals and give on the output a voltage level proportional to the differential phase. This voltage drives the VCO which produces a signal with a frequency related to the input voltage. So the designer set the parameters making the input voltage VCO equals Vdd/2 when the two input frequencies are equal so when there Is no phase difference in the input signals. At VCOinput=Vdd/2 the VCO produces the center frequency which has to be equal to the frequency of the input signal. So the designer makes the locking occuring exactly at VCOinput equals Vdd/2. If the frequency of the input signal increases then the VCO increases the frequency of the output signal making It equal to that of the input signal. The pll is looked but in this case VCOinput Is larger than Vdd/2. There Is a range of VCOinput voltages, so a range of input frequencies in which the pll can follow the input frequency and stay locked. Outside this range pll cannot stay locked.
Hi, Thank you for your comment. I am not sure what you mean. Well, taking away M5 and M6 for a resistor make you loose the current mirroring so the circuit wouldn't work anymore. You could change only M5 with a resistor but this is a CMOS so an integrated circuit. It is difficult create resistor in this technology. You use mosfet for loads (resistance or capacitance). If you want to replicate this circuit with discrete components putting a resistor in place of M5 theoretically it works but in practice it is difficult make current mirrors with dicrete components. The mosfets must be matched and even inverters are difficult because the p-mos has to be double size in comparison with the n-mos in order to have the same transition time (low-high and high-low). Morevover, the frequency would be much lower. I hope I answered to your question
Ring oscillators are not accurate enough for the high frequency of computers. Computers use a crystal oscillators and the CPU multiply the frequency with an internal PLL (because Crystal osc are accurate but they reach low frequency typically 100 MHz)
Excellent explanation. I hadn't even thought of putting the current mirrors on both rails, but I bet that helps with keeping the output levels valid for buffers. Have you looked at startup instability? E.g. with 5 or more stages it's possible to have multiple edges in the system - eventually one will dominate, but until it does the frequency can be faster than expected.
Interesting. I used metal gate CMOS (4000 series) inverters in some very non-standard ways back in the 70s and 80s but I've not come across this.
It is a nice circuit
Hello! I have a question. In type 1 XOR PLL there is 90 degree phase shit between input and output. And when the two signals are at 90, the average output voltage will be half Vdd. I completely get that part. But my confusion is more fundamental here. Why does the locking occur at exactly half the voltage(Vdd/2)? Any constant phase difference means same frequency. But it locks with 90 degrees difference. Why it locks at VCO's center freq?
Hi, pll is composed by a phase detector and a low pass filter which detect the different phase of two input signals and give on the output a voltage level proportional to the differential phase. This voltage drives the VCO which produces a signal with a frequency related to the input voltage. So the designer set the parameters making the input voltage VCO equals Vdd/2 when the two input frequencies are equal so when there Is no phase difference in the input signals. At VCOinput=Vdd/2 the VCO produces the center frequency which has to be equal to the frequency of the input signal. So the designer makes the locking occuring exactly at VCOinput equals Vdd/2. If the frequency of the input signal increases then the VCO increases the frequency of the output signal making It equal to that of the input signal. The pll is looked but in this case VCOinput Is larger than Vdd/2. There Is a range of VCOinput voltages, so a range of input frequencies in which the pll can follow the input frequency and stay locked. Outside this range pll cannot stay locked.
Could we change M5, M6 to a variable resistor instead for some other applications.
Hi, Thank you for your comment. I am not sure what you mean. Well, taking away M5 and M6 for a resistor make you loose the current mirroring so the circuit wouldn't work anymore. You could change only M5 with a resistor but this is a CMOS so an integrated circuit. It is difficult create resistor in this technology. You use mosfet for loads (resistance or capacitance). If you want to replicate this circuit with discrete components putting a resistor in place of M5 theoretically it works but in practice it is difficult make current mirrors with dicrete components. The mosfets must be matched and even inverters are difficult because the p-mos has to be double size in comparison with the n-mos in order to have the same transition time (low-high and high-low). Morevover, the frequency would be much lower. I hope I answered to your question
Is it possible to integrate ROSC in processor
Ring oscillators are not accurate enough for the high frequency of computers. Computers use a crystal oscillators and the CPU multiply the frequency with an internal PLL (because Crystal osc are accurate but they reach low frequency typically 100 MHz)
It looks like Ring oscillators
So this is ah! PLL
👍
I wish I could hear what it sounds like.
Yeah, that would be awesome. I wonder what the limits to something like this is. What other designs there are.