[Eng Sub] TSMC SOIC

1. TSMC SoIC?
2. Process
: Step 1. CMP (Chemical Mechanical Polishing)
: Step 2. Surface Activation by plasma
: Step 3. Chip to Chip Bonding for dielectric material bonding at room temperature
: Step 4. Anealing for Cu to Cu metal bonding at high temperature
: Key machine suppliers - EVG, SUSS MicroTec, ASM Pacific, Besi, and Applied Materials
3. Applications
: Sony Image Sensor
: AMD 3D V-Cache

[@semicontalk3223]

Typo correction - At 1:24, Cu Piller --> Cu Pillar
Error: At 3:38, I repeat same sentence 2 times

[@younsookim4790]

Hi, I always love to watch your video which is really helpful for me to understand the PKG area. One quick question. For the CoWoS-S, Do you know how many Metal layer is being used(MaX) for the S-interposer? Are there any limitations to increasing the number of metal layers or is it just a matter of cost issue?

[@semicontalk3223]

TSMC CoWoS usually uses 3~5 metal layers on Si interposer depends on configuration. There should be maximum number of metal layer on Si interposer because there should be minimum width of metal trace. But typically metal layer is limited by manufacturing cost.

[@m_sedziwoj]

Could you make video about InFO_oS which is probably use in Zen4 because for some reason I don't see where this technology is use on official TSMC documentation. Where are connections?

[@semicontalk3223]

Sure but nowadays I couldn't make video without time. But let me explain little bit about InFO_oS. InFO_oS is InFO on substrate means fan-out package with multiple dies attach on package substrate. Die to die connection is done by RDL without micro bump and InFO package to substrate is connected by Cu bump. Solder ball is located on the bottom of substrate. For InFO fan-out package, solder ball is located on the bottom of RDL. I think InFO_oS is for HPC(High Performance Computing) application with larger package size and advanced fan out interconnection technology of InFO.
3dfabric.tsmc.com/english/dedicatedFoundry/technology/InFO.htm
Please check slide 9 and 10 of below presentation file from TSMC.
hc33.hotchips.org/assets/program/tutorials/2021%20HotChips%20TSMC%20Packaging%20Technologies%20for%20Chiplets%20and%203D_0819%20publish_public.pdf

[@testuser902]

If there is dishing on top of the copper pads where does the material come from to fill that gap. If it is aniline is done when heated then would it not shrink back down when it colder and crack?

[@semicontalk3223]

Fill that gap is done by Cu volume increase by temperature increase so no material come from outside to fill that gap. Cu does not shrink back when it cool down.

[@RuiYuan-dl8wm]

Can you explain more why Cu don't shrink back when it cool down? It's a little confused.@@semicontalk3223

[@jugen123123]

Thanks for sharing, It's a challenge to TSMC SoIC.
I wanna ask how bump stress become while bump density increases

[@semicontalk3223]

In general, it is increased because of smaller bump. But we need to consider many items to be accurate.