verilog code for fulladder

[@rivughosh4814]

Sir, why aren't you using MSB and LSB feature in source wizard window and denoting input or output ports??

[@sampathkumar7149]

Explain the Implementation of full adder using cmos logic in verilog sir

[@SaswatiSamanta-ld3ms]

VHDL for full adder using module
approach and this code are same?

[@knowledgeunlimited]

There will be slight difference in the syntax , there you will also add syntax similar to C language syntax.

[@circuitsanalytica4348]

YES, there is similarity in the approach. In VHDL we have to declare the module as a component in the declaration part of the architecture. In Verilog, no need to do the declaration explicitly....

[@prakruthimc721]

In which software are you doing sir

[@knowledgeunlimited]

Xilinx

[@tejashr6470]

Sir ,can u please share the code

[@adnanjamilhashmi3679]

Can I share my link?? On your comments box

[@knowledgeunlimited]

If you feel , it helps you , you can it's not an issue to me.

[@bbgswm4455]

감사합니다

[@goldenffshorts]

Toooo much blur I can't understand anything

[@knowledgeunlimited]

Sorry for inconvenience.