VHDL Lecture 18 Lab 6 - Fulladder using Half Adder

[@awaisumar5125]

please correct one line...at 16:42 we will map A=>sum1
not A=>C

[@EDUVANCE]

The line is correct. You can also assign A, the third input of full adder.
i.e. A => C
B => sum1
In this case vice-versa can be also done. i.e. A => sum1 and B => C

[@shubhamupadhyay5596]

very helpful