Most asked Verilog Interview Questions - part2

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  • Опубликовано: 26 янв 2025

Комментарии • 6

  • @MANISHKUMAR-ee2ty
    @MANISHKUMAR-ee2ty 11 месяцев назад +1

    In question 14, #1.24 *10 = 12.4 but it should be approx 12..

  • @ankitsinghyadav-ld9gw
    @ankitsinghyadav-ld9gw Год назад +1

    for q14, statements are non blocking , still you are adding delays?

  • @ravishankarkiriti8444
    @ravishankarkiriti8444 10 месяцев назад +1

    hello ma'am what is the answer for 5th question force and release ?

  • @sSODISETTIGAYATRI
    @sSODISETTIGAYATRI 11 месяцев назад +1

    module top();
    function xyz( input int a,b, output y);
    y=a&b;
    return y;
    endfunction
    initial begin
    bit x,y;
    x=xyz(1,1,y);
    $display("x=%0d",x);
    end
    endmodule
    Mam u said that don't pass output as an argument then it shows an error but in above code no error is occurred and I shows the correct output

  • @hanu5090
    @hanu5090 Год назад

    for 15th question option--b is correct 10567