State Table and State Diagram for J-K Flip-flop

This video explains the state diagram, state table and VHDL code for J-K flip flop.
Dr. A. V. Thalange
Associate Professor,
E&TC Dept.,
WIT, Solapur

[@melihturkoglu9892]

JK state diagram can be drawn without knowing Q, it does not matter if it is 0 or 1. Easily for JK, If JK is (0,0) there is no state change, present = next, if (1,0) then whatever Q was, Q next is resetted as 1, when ( 0,1), it is setting 0 whatever the present value is, finallay for (1,1) it toggles the output meaning that if present was 1 then output is 0 , if present was 0 then output is 1

[@plutomessi21]

thank you so much

[@pamp3657]

good video thank you

[@chandrakalachauhan470]

Thanks ma'am

[@setfrd]

what did she say at 5:33

[@alexzandergingras7742]

Look at those red lines. Each of them represents a transition. The first line she mentions represents the present state being 0 and the next state breing 0. In that transition, we see that two things can cause that: J,K = 0,0 and J,K = 0,1. When we compare both of those cases, we see that regardless what K is, if J = 0, we'll get that transition. Then we go through all the other transitions and compare each case to get similar results

[@manikyalaomanikyalarao7693]

Voice is low

[@Bhagavadgita-py6gz]

We want English subtitles