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if this is inverting opamp then it is -rf/rin right?? why are you using (1+rf/rin)

Both of you solved the second question incorrectly. You guys didn't take the effect of initial condition on the capacitors into consideration. [ Vc1(0+) = 3.5V and Vc2(0+) = 1.5V ---> Assuming equal capacitances.] There should be an errata video of this instead of just letting it go, if you really want people to learn as you said in your video and not make silly mistakes like you did.

How the pole is at zero frequency can you explain ?For last question.

Hello Sir, The 2nd RC ckt you gave in which the initial conditions of capacitors were +1V and -1V. At t=0+ the Vo will be 1.5V and can be calculated using Qi=Qf on the capacitors and then Vo(t) = -u(-t) + (5 - 3.5*exp(-t/2RC))*u(t) and Vc1(t) = u(-t) + 3.5*exp(-t/2RC)*u(t). I also confirmed it on simulation.

Good video!

Thanks Sir 👍 Very interesting circuit 😊 Guess [(v+-v-)*A-vout]*1/Rout=voutsCL....T.F(1) with no feedback (diff pair with active current mirror) Rout=ro2//ro4 A=vo/vd=gm*Rout Vin=v+-v- 🤔 The version is so merciful to Man! Case1 db=20(1-log2) almost 13db Case 2 Cap have a initial value and my vc1 discharge and vc2 - 1to 2.5 and then exponential increase charge close to 5v waveform is the same as You Very interesting circuit 😁

As the current in the inductor ramping up with time after 9 sec that current must exceeds 9 A which tells that n side of the diode voltage is greater then 9 v slightly which eventually make diode to turn off that mean drop across diode is 0 ? If that is true then drop across inductor become 0v which makes current through inductor also 0A according to the equation of inductor?

quasi differential amplifier using cross coupled CMOS inverters 🤔

Thank you Sir 👍

Can you explain the polarity of the gain. the polarity of the gain should be negative. according to your analysis, if the parallel R is negative, the gain is positive?

Thank you Sir 👍🙏

Waooo too good questiom

Thanks Sir Very interesting with Simple conpect circuit ☺️

Thank you Amit, this mock interview truly boost my confidence to get job as an analog design engineer.

Explaination in detail and it is very interesting circuit 😁 Thanks Sir

if you know that cross coupled pmos provides +ve feedback. Then intuitively it can be said directly that gain is infinite.

Very well explained, thank you Sir👍

Nice explanation and it is very interesting circuit 👍 P_Mosfet is cross-coupled with the inverter and has two capacitors C1 and C2 respectively. So with a tiny resistor -2/gm, we can easily understand the charging and discharging results of C1R charge , C2R dischargeand of the output and the other inverter, There are Hi to Lo and Lo to Hi circuits when we input The signal is pulse or u(t)... Very simple 😊 Are parasitic capacitances not considered in the actual design and layout circuit design? 🤔

what's the purpose of this circuit? is it useful in any case? or just useless circuit created for you to analyze?

Thanks Sir Excellent explanation,😁 Simple and it is very important conpect

Thank you sir

the brief answer is, it is widely used because of: - Impedance matchning: source follower has low output impedance which means it has the ability to drive low-impedance loads with signal attenuation - wide bandwidth: this is a bit trivial as miller effect is negligible as the gain is approx 1, thus the input capacitance Cin=Cgs + (1-Av)Cgd ~ Cgs and other things such as signal level shifting, stablity and linearity

Phase plot should start from 180 degree and eventually reaches to 180 degree since it is a common-source amplifier.

you can explain this in a much simpler way if you were to just derive the transfer function; which is (Vout/Vin)=Gm.Zout=Gm(R+1/sC)=Gmx(1+sRC)/sC and from this it is then obvious that there is pole at zero, and zero at -1/RC!

Great explanation,Sir! 👍 Can you derive common mode gain,vo swing (max), vo swing (min), vi ICMR（max), vi ICMR(min) 🤔

Can you derive common mode gain?

Hi Amit, Could you suggest the any NPTEL course for Analog Circuit Design for similar to your videos which would be very helpful for certification.

so helpful videos

Thank you Sir 👍 Very interesting circuit of RL!😁

Sir your videos are very informative...thanks alot sir ... please Continue This series ❤❤

Nice explanation, Sir👍

Nice elaboration thanks 🙏

Hi Amit. Thanks for sharing the knowledge. but can we gain more by changing the w/L ratio in this circuit? Vout= gm*Rout.

at the end , the end condition will make mos on again ( opam out voltage 5 v , Vds for mos =(5-0)v and VGS=5 V) so will happen next ( on - off- on - off)

No use at all…mug n vomit country…no practical education in schools and colleges. Just mug n vomit in exams for marks to find 3rd class job thinking you have achieved a great feat.

Thank u ❤

well explained👍

Nice explained sir I have a doubt that if +vdd is given 6 volt and -vdd is given -7 volt then at which value output voltage will be saturate?

Hello Sir, Thanks for your video. What is your reference for this interview questions? How can you access them?

How C1 & C2 are considered in series while finding the timie constant? You mentioned that we need to find the cap connection across the Req but did not understand it how they will in series in that case? Is there any simple approach to understand that?

Hello Sir, I hope you don't take my comment in wrong sense. But if you can relax a bit while narrating and use fillers like "Okay" bit less in your speech, the narration will sound much more pleasing to the listener. Currently, even though your explanation is awesome, the filler sounds feel odd and irritating to hear.

amazing explanation sir thanks

Very detailed explanation！ Thank you Sir🙏

would it not be negative

guess！ Remove the two 2-diode first, then vo is approximately 7.1, D1 on, d2 off, so vo-10=-vo/9,9vo-90+vo=0v,v=9v..Answer

The current Ix equation should be of linear region right? as device is in linear region at that point