STA Lecture 4: 10 ways to fix

In the industry, timing analysis is performed at every level of the ASIC design flow, and various techniques are used to address timing violations at each stage. For example, changes can be made at the architecture level, RTL level, and physical design level. It is crucial to understand how these techniques are applied to fix setup violations in the design.
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[@TianyunHuang]

Thank you! Your clarification is very helpful and made the concepts much easier to understand

[@VLSICareerCraft]

@@TianyunHuang Thank You

[@Kuu797]

Hii madam,
Can you make video's on timing exceptions Multi cycle path, Half cycle path , False path and also videos on how to reduce congestion in different ways.
If we get these videos by this Saturday then it will be very help for me, if not possible it's okay madam.
Thank you for such wonderful content.

[@VLSICareerCraft]

@@Kuu797 Sure , will do some videos on these . These are really great STA topics.

[@Kuu797]

@@VLSICareerCraft Thank you

[@sivareddys2313]

when the size of a gate increases,the capacitance increases . So the RC increases, then how come it decreases the delay ?