Very grateful for this dissection of the process. This is a great example of good teaching where you've taken something really complex and broken it down into small chunks which are easy to take in. Bravo, dude.
The IPv6 protocol does not use header checksums. Its designers considered that the whole-packet link layer checksumming provided in protocols, such as PPP and Ethernet, combined with the use of checksums in upper layer protocols such as TCP and UDP, are sufficient.
I have been watching about since about years about fetch-decode-execute cycle,but I haven't catch a significant points comparing with the time I consume. What is the prior topic I should attend to understand well.
in this case operand shows the content to be added on, but sometimes CIR holds opcode+ Address of the content that the instruction is to be executed on. how to identify that?
I think it was alread there, it was loaded there in the previous instruction that obvious wasn't showed in the video, and when an instruction has ADD as an opcode, it means that it has to add whatever there is in the accumulator, with that operand of that ADD instruction.
+Comp Franklin So the CPU fetches the instructions from the RAM via the address bus and the instruction (after being fetched) is sent back to the CPU via the data bus?
@@memelord9965 The address bus is just for selecting which address in RAM to work with (read or write). The data that is read from or written to RAM travels across the data bus. Everything in the diagram - other than main memory and the buses connected to it - is the CPU. So when an instruction gets to the Memory Buffer Register, the instruction is in the CPU.
Very grateful for this dissection of the process. This is a great example of good teaching where you've taken something really complex and broken it down into small chunks which are easy to take in. Bravo, dude.
A kiss and a hug for you from Manila. You just made this lesson very simple. You are an angel!
Thank you. It is easy to understand the cycle when i watch your video
OH GOD .. YOUR'RE THE BEST TEACHER
THERE ARE NO WORDS ENOUGH TO THANK YOU .. BUT THANK YOU
Nice simple and thorough, thank you for uploading.
This is extremely helpful, thank you!
Thank you. Very much helped to understand the machine flow.
Great, Very good. The best diagram that i saw!
Thank you very much, very clear and understandable.
Extremely helpful!
terrific explanation. bravo!
Thank u so much,for such a clear explanatio.
The best explanation I found. Thank you!
Perfect VIDEO!!
Great video man, love you!
GAYYYYYYYYYYYYYYYY
explained very well
thank you
Thanks bruv! Helped me a lot!
best explanation ever on this topic
i was totally clueless before i found this
i love you man you're a lifesaver XD
great diagram!!
wow nicely done,very understandable
was having a hard time getting my way round the whole process
pun
really awesome
sir
thank you its best explain ever
thank you so much !
man your a life saver i have a 400 word essay based on this
thank you, youve helped a lot
Have my A levels exam in around 12 hours and here I am resorting to youtube...
Same dude lol
why do we do this to ourselves
xD same
nice and clear
very entertaining vid, helped me in ,my studies
The IPv6 protocol does not use header checksums. Its designers considered that the whole-packet link layer checksumming provided in protocols, such as PPP and Ethernet, combined with the use of checksums in upper layer protocols such as TCP and UDP, are sufficient.
brilliant bro
thanks buddy
I have been watching about since about years about fetch-decode-execute cycle,but I haven't catch a significant points comparing with the time I consume. What is the prior topic I should attend to understand well.
just the best of the bests
in this case operand shows the content to be added on, but sometimes CIR holds opcode+ Address of the content that the instruction is to be executed on. how to identify that?
wheres MDR?
awesome video but one question...! How did four get stored in the accumulator??
I think it was alread there, it was loaded there in the previous instruction that obvious wasn't showed in the video, and when an instruction has ADD as an opcode, it means that it has to add whatever there is in the accumulator, with that operand of that ADD instruction.
I have the same question
wheres memory data register? is it essentially the memory buffer? If someone could help it would be greatly appreciated i have exams soon.
different names 4 the same thing
Does the CPU fetch the instructions from the Hard Drive or does it fetch it from the RAM?
+john rear fetches from RAM - instructions are also loaded into RAM from any secondary storage device still via data bus
+Comp Franklin So the CPU fetches the instructions from the RAM via the address bus and the instruction (after being fetched) is sent back to the CPU via the data bus?
@@memelord9965 The address bus is just for selecting which address in RAM to work with (read or write). The data that is read from or written to RAM travels across the data bus.
Everything in the diagram - other than main memory and the buses connected to it - is the CPU. So when an instruction gets to the Memory Buffer Register, the instruction is in the CPU.
did not expect to see a guy called meme lord here
great
Is this according to O Levels??
if the number of bits of oprande adresse is less than number of bits of the processor registers than how processor of 32 bits can adressing 4GB of RAM
A level students here hehe;)
+Keelan Letsplay Sitting for the October/November Session?
No no, i'm a first year computing student I started in September.
Thanks man
Thank you fo the moist explacitojsdpfj[apjdfs
1:16 British accent and One direction
1:55
Who else is here from homework haha
Ello there mate chances of seeing you here lmao
good
you sound like youre in a hurricane
Holy shit, u speak slowly. -.- 1.5x is like normal speed.
Slow and boring, hard time paying attention to it