3-Bit & 4-bit Up/Down Synchronous Counter
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- Опубликовано: 1 окт 2024
- Digital Electronics: 3-Bit & 4-bit Up/Down Synchronous Counter
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Anyone is from 2024 😂
Here😂😂😂😂
😁
Fck it was 9 year ago
I'm 2050
Yes
who is watching this just before their exams !!!!
Me
Me too
We all are 😂:)
Me too lmao i have mine day after
🙋
you saved my life from the hell of assignments. praise you.............!!
Same bro
+1
Can we do the same 3 bit updown counter using D ff
++1
Same bro
OMG MY TEACHER LITERALLY GAVE ME THIS ASSIGNMENT ABOUT THIS AND I HAD NO IDEA HOW TO START, THANK YOUUUU
same here
13:06 small mistake here
It'll be
TB = M'Qa + MQa', you wrote MQa
And therefore M exor Qa
😅👍🏻
This quarantine era you need this kind of online lecture, neso academy is where I go when having problems related electronics lecture. Thank you !!!
Even outside of quarantine, this guy teaches several thousand times better than professors
Hello. I suppose you have made a mistake deriving a boolean expression for Tb. The second operand should be MQ' instead of MQ. Correct me if I'm wrong
Yeshh..you are right ..because my ans is also this..bt i was little bit confused..thats why i open the comments bt no one had write..finally i found one of my type..🥹❤️
While making ckt. diagram he had corrected guys, see full video
Tommorow I have my digital electronics exam tysm 😊 your lectures so good keep going!!
how to draw kmap if it has 4 bit ?
Sir you didn't tell whether it's up counting or down . I confuses now somebody plz help!
sir you are awesome.....i cannot get it properly in my college but when i see ur videos lectures i get compeletly familiar with every aspect discussed in videos.......ty sir ty so much
Hi, why don't you just use XOR gate with M & Q as inputs so if M=0 then output is Q ➡️up counter
and if M=1 then output is Q complement so ➡️down counter
I think this is easier
You didnt get it. Now what is situation
anyone in 2019 ?
2024😂
it should be M'Qa+MQa' @13:12
Everyone needs to see this ^
I m from NIT surathkal , I just watch your lecture 1 day and I complete my all coa syllabus
Thnx buddy
dude seriously
Kindly check the truth table for down counter as per state diagram which is start at 8.35. I have some doubts it seems that it counts up.
I have a question, why didn't you used two XOR gates for T² and T³ equation? It would have been more neat and simplified!!!!
Thank you so much to that 10000% clear understanding ❤️❤️❤️❤️
13:00 Hey how is *MQa + MQa = M XOR Qa ?
Hmmm you are right... it's a mistake here
16:28 he realises the thing
What if we directly use xor gate to get Tb (17:10)
Sir you are really better than paid apps You are teaching greatly for no cost. Keep Teaching.Hoping 5M subscribers.
This has literally helped me so much thank you for your demonstration and teaching!
u look so beautiful
@@jaspritakash5152Bhai kuch to rakhle Indian hone ke naate😂
How were you able to infer the pattern to construct the 4-bit Up/Down Synchronous counter without creating another truth table with 4-bit states?
+Annie Chen irriatative design technique
sir, at 13:04 , there will be MQ' instead of MQ.
Correct !!
I have watched 43 videos from last day I didnt hear any voice except your voice .
sir, i think a(xor) b= a'b+ab ' i.e M'Qa + MQa not equalls M(xor )Qa . it is formula we use for caluclating QB IN ABOVE LECTURE. please check it.
Does anybody else have an issue from state diagram
It should be 111 to 110 but instead we wrote 000?
Thanks sir for this lecture but please tell how can be draw k map for four bit synchronous up down counter
***** pls explain and give example of lockout in synchronous counters.
The truth table for down counter is incorrect under Next state and under Flip flop inputs, you wrote 001 after 111.sir don't you think in case of downcounter after 111 we should have 110
Thanks sir for clearing doubt. I apologize for the mistake.
But sir again there is upcount for M=1
How could it be possible
thanks for help me sir...i like your study method .plz sir give me the technique to convert 8 4 -2 -1 code to binary...
Thank u so much sir. This lecture which u were saying is very informative and useful.
Hello !
Thank you so much for the videos
They are really helpful
Can I ask a question though ?
what is the program that you use to write ?
This is transition table this method is used to fine the input of flipflop
This table is vary depending upon flipflop's excitation table
Everyone need explanation like this... Awesome neso academy 🙂
Thank you so much!! it helped me a lot perfect teaching!
U deserve millions of subscribers. I have been watching your videos since my first year! Now I m in my fourth and going to be graduating. Thank you alma mater💓
are you studying this subject in fourth year
No, was revising for my interviews.
@@akankshyabhattacharyaa7008 oooo thats great so how was your interview
@@akankshyabhattacharyaa7008 You were supposed to continue the conversation with my boy adil :(
@@Dawood_Awan currently employed with the company and replying admist work 😆😆
how to do k map with 5 bits??(m,a,b,c,d)
Why don't you use Ex-OR gate for implementing T(b) = M Ex-OR Q(a) in the implementation of this counter.
for down counting after 111 it has to be 110 right, you have written 000
no it is actually 000 bcz at left the present state is 001 so the next state will be previous one of 001 i.e.000
How do I construct the K-map for 4 bit synchronous up/down counter?
It would be much more helpful.
@080 Sekar M lol same question
Did you get this now?
ktu students undoo??
THE REAL FUN STARTS WHEN YOU SEE THIS VIDEO AT SPEED=0.5 xD !!! MUST TRY !!!!
lol
actually lol
lmao
Raju rastogi lol
it works for up counter , how not for down counter ?
in down counter when present state is 0(000) the next state should be 7(111) , and when it is 1(001) next state should be 6(110) ... but yours next state is again starting from 7(111) then o(000) then 1(001),and so on like up counter ... Please answer . tnx
+niamatullah bakhsh as we know in down counter next satae=present state-1
so as per my p.s=1(001) so my n.s =1-1=0(000)
Please check the sequence once again as up down counter means count from 0-7 and agian 7-0 .
8 years ago and this is giving me all what i need today
Sir Plz tello .
How to make BCD Up/Down sychronous counter....
Plzzzz tell
What about 4 bit synchronous counter truth table and K Map.
Why not just use a 2-1 multiplexer with M as the selector input?
nice thought man very very nice!
because in an exam you can't do what you want :L
Shuki Shan 😃
@@shukishan 🤣🤣
i dont understand why we're taking such huge complexities
just take the ones compliment of the results of up counter
use xor gates with M before every Qi (i=1,2,3)
if M is 0 output is Qi ...... counting up
M=1 gives (Qi)' ..... counting down
I am watching after my exams😅
How can I design a 5 bit down counter but I want it to start counting from 20 down to 1 (I mean, I don't want the counter to start from 11111, using all 5 bits), Does anybody know how to do it? I have no Idea, I'll appreciate it
@13 minutes , i didnt understand , on For Tb u said m(cmpli)Qa + MQa, isn't Qa supposed to be Qa(compliment i mean Qa is not changing and is represented by 0 0 then it must be a compliment isnt it)
Nothing to say... Lots of love from anantapur Andhrapradesh
Sir!
Is 3bit sync up/down counter and 4bit sync up/down counter same?? Or in this presentation you did only for 3bit?
Why does 3bit asynchronous up down counter have 2 inputs and 3bit synchronous up down counter have 3 inputs? Please help me. Getting confused.
sir, at 13:04 , there will be MQ' instead of MQ.
*14.02
yeah thats true
students like you make me love youtube… keep it up
Let if be man, is still fine the XOR gate
he fixed at 16;33, u did not see the whole lecture sir?
this is amazing i understood everything! thank you very much :)
I like your tutorials, they are quite helpful, however, I think you should re-verify that the down counting truth table is correct.
+Michael Eze completly correct
+Michael Eze Dude i had the same doubt... the downcounting is absolutely correct.. For more clarity... when m=1, try writing present state frm 111,110,101 downwards.. nd form the next states accordingly..!!
I still don't understand this part. Even though m=1, the count is going from 111 - 000 - 001...
It's just one step backward and continues counting up..
@@yeshwanthreddy9450 You need to look at it like this. When the present state is 000 (0) it goes to 111 (7). When the present state is 001 (1) it will automatically go to 000 (0) and so on down the truth table. Its basically just saying when that present state is for example 010 (2) please go down to 001 (1) to become the next state.
@@nickthewinner2194 What you said is absolutely correct but isn't the down counter suppose to count like 7,6,5 etc upto 0.Here the sir has just decremented the next state
please solve 4bit synchronous binary up counter
PLS
Is 3 bit and 4 bit are same?
Sir the thing you said at end of lectures does it really work for 4 bit up/down counter ?? and in which stage will it act as up counter and down counter ??
does this idea of going from 3 to 4 bits extend to 4 to 5 bits aswell?
How we can k map because we have 5 inputs m,q3,q2,q1,q0 in 4 bit updown counter
Y r we using T flipflop for 3 - bit whereas jk flipflop for 4-bit synchronous counter
Only legends know which game is at 11:56 😁😉
can you please upload videos on synchronous BCD counter and Up-Down Binary counter ?
At 13:00 T(b) should be equal to Q(a)
Hmm
Sir ,for 4 bit asynchronous up and down counter do we have to take 15 up counting and 15 down counting??
What about jk f.f up down sych..... How i will do the output of oR gate to any j or k??
In the context of synchronous up/down counters, toggling refers to the action of changing the state of a particular bit in the counter. Specifically, toggling involves switching a bit from 0 to 1 or from 1 to 0 right ?
then how you are always writing 1 when toggling ???
Can you help me in this question "A digital computer has three registers: A, B and C. Four flip-flops provide the control functions for the computer: S is a
flip-flop that is enabled by an external signal to start the
system’s operation; L and R are used for sequencing the microoperations; A fourth flip-flop T is set by the computer when
the operation is completed. The function of the system is described by the following register transfer statements:
S: C ← 0, S ← 0, T ← 0, L ← 1
L: L ← 0, if (A = 0) then (T ←1) else (R ← 1)
R: C ← C + B, A ← A - 1, R ← 0, L ← 1
Design a circuit with minimum components to implement the above operations."
sir your explanation is best 👍👍👍, i can't understand another video. Sir you able to create synchronus up down counter usnig D FF ? I Always waiting for your reply , so sir reply me
i have become this task
(Design a 3-bit counter with synchronous D flip-flops with outputs Q3, Q2, and Q1, which counts up at E=0 and sets all output values to 0 at E=1.)
and i try to build the state Diagram.
Is it the same principle with Down counter ( Thank you Sir)
Hey at the end just check out jk flip flop is positive trigger right..
If we use jk flip flop what will we have to fill in table for j k?
i think for 4 bit up down counter we solve 5 variable k-map yes or not
What if the truth table for J0 was all of it X and K0 was 0 what will be the final soultion??
I am confused with propogation delay in synchronous counter..how it can be Tpd when one every flip flop needs previous output??
Consider a 3-bit synchronous counter with 3 flip flops. Let's say their outputs are Q1, Q2 and Q3. Let's say the initial state is 000. It's important to understand that all the 3 flip flops have inputs present to them to be processed at next clock pulse. Output of FF1 is Q1 which(or some logic of which) is input to FF2. Similarly, o/p of FF2 is Q2 which is input to FF3. And Q3 is output of FF3. All these three outputs Q1Q2Q3 change simultaneously due to the synchronous clock. As the Flip Flops always have the required data present at their inputs, they just need the clock pulse and take Tpd delay to change the output.
where is outputs and why not just use Qa' , Qb' , Qc' for down?? and then take Qa , Qb , Qc , Qa' , Qb' , Qc' as 6 outputs ; we simply get an up-down synchronous counter easily !
If we want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip flops required to implement this counter is ???
can you please explain ..
Sir down counting me to hame state diagram ka opposite jana hai na aur jo velue aye wo likhna hai
Sir your teaching is very helpful ,plz continue like this only ☺️☺️☺️
Thanks. How can i design same counter with D- FF.
Is there a difference of implementation between a synchronous counter negative edge triggered and a positive edge triggered?
no afaik
how to make a bcd Counter? After 1001 its next is 0000, after this do i have to take others(i.e. 1010 to 1111) Dont care (X)??
name should be only 3 bit ..bcoz only 3 flip flop are used
if I need to truncate a counter, how it would look like?
thank you so much for your teachings, they are very helpful, gratings from Spain
I hope I will not fail this electronics exam on Friday!
have a doubt if the question is design a 3 bit up down counter which counts up when m=1 and down when m=0, which one to use synchronous or asynchronous?? need an solution asap
Why don't we use XOR gate directly...?
please check the down counter,QA',QB',QC'
Why did u take 'A' as MSB and 'C' as LSB?
In the immediate previous lecture, it was other way round.
Sir,how to do synchronous random sequence counter like if we give 0,3,1,2,0,3,1,2,0 and so on how to do these type of problems
In asynchronous we have used logic 1 for jA and kA ,jB and kB also for jC and kB
But in synchronous why should we place input to kB and kC with inputs of OR gate
Hello
How can you help I design synchronous down counter by using 4 T flip-flops?
Please ..
3bit syncronous up/down counter ki o/p kase len gy
Thank You for your guidance 🛐
Shouldn't K be connected using not gate by J in the last?
I got Confused the way you explained from 8:40 to 9:12
*Sir SR flip flop or RS flip flop ki truth table, characteristics table and truth table m koi difference h kya???*