7-Segment Display using Verilog and DE10-Lite FPGA Board

[@CarlosHenrique-gx9hx]

Great video, thank you for sharing, it helped my class, our experiment was to use the 7-segment display to display the result of a 4 bits sum

[@Dyrl.a]

lol have a big lab practical tomorrow and this is a god tier video tbh

[@udaykumar-be4gg]

Hello Sir,
I am using the DE10-Lite board and would like to know how to load a program into the flash memory so that it persists even after the board is powered off.

[@saifUllah-q4e1c]

module mux(
input wire a, b, c, d, // 4-bit input as individual wires
output wire [6:0] s // 7-segment display output (active low)
);
reg [6:0] segments; // Internal register to hold segment states
// Continuous assignment to connect segments to output s
assign s = segments;
// Always block to evaluate on changes to inputs a, b, c, or d
always @(a, b, c, d) begin
// Case statement to determine segments based on binary input
case ({a, b, c, d})
4'b0000: segments = 7'b1000000; // 0
4'b0001: segments = 7'b1111001; // 1
4'b0010: segments = 7'b0100100; // 2
4'b0011: segments = 7'b0110000; // 3
4'b0100: segments = 7'b0011001; // 4
4'b0101: segments = 7'b0010010; // 5
4'b0110: segments = 7'b0000010; // 6
4'b0111: segments = 7'b1111000; // 7
4'b1000: segments = 7'b0000000; // 8
4'b1001: segments = 7'b0010000; // 9
4'b1010: segments = 7'b0001000; // A (10)
4'b1011: segments = 7'b0000011; // b (11)
4'b1100: segments = 7'b1000110; // C (12)
4'b1101: segments = 7'b0100001; // d (13)
4'b1110: segments = 7'b0000110; // E (14)
4'b1111: segments = 7'b0001110; // F (15)
default: segments = 7'b1111111; // Blank (all segments off)
endcase
end
endmodule

[@zhaoyangxie]

Are the individual segments replaceable? The top part of one of mines went out

[@educationdz202]

Yes, you can change the faulty seven segment display, and it's a common anode type.

[@amsab2365]

that is briliiant could you share the code please

[@ncorasaniti4868]

That's actually really cool

[@nantes9807]

thầy ơi, thầy là người Việt hửm thầy.