Verilog in 2 hours [English]

[@TusharKumar-iu4nt]

A really descriptive video on how to write verilog codes... Even a beginner like me was able to understand what lies in this intriguing topic in a single go!

[@faisalkashif2011]

A topic at the core of digital circuit design, covered by an expert of the field.

[@riyakhera5665]

Outstanding presentation. Never seen such a good projection of a topic.🙌

[@RenzymEducation]

Thanks a ton

[@return2Quran]

Much needed short course. Thank you.

[@sridevia4819]

Thank you so much sir for this wonderful basic video which helps a lot for beginners like me

[@matindarakhsh]

that's all i needed
thank you!

[@mdomarfaruque493]

You did an amazing job brother.Jazakallah

[@RenzymEducation]

Thanks a lot

[@1800haseeb]

Sir kindly give 1 session on VHDL as well like if we know Verilog how we can do programming in VHDL as well. I tried to understand it but its bit different and there are some differences which I am not able to understand in perspective of Verilog. Like this session if you can give VHDL session as well it will be great. Thank you so much

[@saurabhr9017]

Well I will be Honest it's not for absolute beginners, rest he is doing well

[@swetathanu8253]

thanks sir. A clear and best video for Verilog and more

[@RenzymEducation]

You are most welcome

[@williesolomon614]

Very impressive tutorial. Thank you for sharing this to us..

[@aleXelaMec]

Thanks for a great video. Was very useful for me!! If youll have more, it would be great. You are explaining very good. Maybe come more complex example. (In english)

[@RenzymEducation]

A little bit complex design example (in English) is that of a small processor
ruclips.net/video/HCzIK322Pzw/видео.html

[@aleXelaMec]

@@RenzymEducation too many steps ) but ill check. Thanks

[@jaysingh6066]

paji tusi great ho, nice video. please make video in punjabi on Intel Altera FPGA also, thanks !!

[@RenzymEducation]

Meri punjabi koi inni changi nai

[@MuhammadIrfan-ox4ud]

May I please get this ppt, for teaching purpose? Thanks a lot.

[@sharathrajm7663]

A heartful thanks to ur work

[@kashifshah3183]

Excellent video

[@ayrtontv6025]

Wow this was so helpful thank you so much

[@saidulsayem9193]

Thank You !!

[@RenzymEducation]

You're welcome!

[@MCCreativeLegends]

Thank you so much 👏

[@thomasmccluskey2217]

Hi, thank you for the informative video! Would you be able to provide the entire code for the state machine please?

[@RenzymEducation]

I have added a Solutions folder with the slides link (tinyurl.com/verilog-slides ) that has FIFO and state machine code

[@thomasmccluskey2217]

@@RenzymEducation Thank you!

[@jsbadhon]

@@RenzymEducation sir this url is not working

[@RenzymEducation]

@@jsbadhon Try now

[@Adilamjad]

Good lecture!!

[@SMITPATEL-px7um]

hello ! can you please provide me reference code for amba ahb lite protocol for my research purposes thanks !

[@animeshsrivastava5067]

Please can you design a course on System Verilog and verification through it via UVM? It's not available fully anywhere and may help us a lot.

[@RenzymEducation]

It might take a while as I haven't used system verilog

[@animeshsrivastava5067]

@@RenzymEducation Thank you so much for the reply. Additionally, please can I request for verification through Verilog videos. In general, the linear test benches are not considered for complicated circuits and other TBs are also present. It'll be great if you can guide on this topic.

[@christonfredrick]

At 8:30 , when the enable signal is on the rising edge, the output shouldn’t 4 also be coming as output? Or does the output starts in the falling edge of the enable signal?

[@RenzymEducation]

Enable is probably drawn a bit wider on slide than it should have been. It was supposed to start rising after rising edge was passed and is sampled at next rising edge. That's why output starts at next rising edge.

[@christonfredrick]

@@RenzymEducation Thanks for the clarification!

[@marwanal-yoonus280]

Dear Sir
Thank you very much for this helpful video
Please, I try to write the following Verilog code in Vivado, the synthesis process is OK but when I want to implement it an error signal appear !!
module Tog_not (hsync, EOL, q);
input hsync, EOL;
output reg q;
always @ (posedge hsync)
begin
q

[@snezestudiesandbeauties5815]

You are not mention clk as a input

[@marwanal-yoonus280]

@@snezestudiesandbeauties5815 Thank you very much for your answer.

[@oatsthedog]

Okay but how do you download verilog? Where does it take place?

[@RenzymEducation]

There is a link to install iverilog (its also there in video description)
ruclips.net/video/Y0bNVStZok4/видео.html

[@joecox9958]

your sound echo not very clear, do you use speaker phone?

[@RenzymEducation]

It was recorded using laptop's mic during covid days

[@kunchemanikanthaswamy1106]

Voice clarty is not good

[@vikramadityatechchannel8118]

sir do you have sdr transmitter code

[@PC-pw7hv]

If you got SDR code. pls share

[@FlorencioButler-v4y]

Rodriguez Lane

[@VincentWiderski-x5b]

Josephine Tunnel

[@editz3420]

Bro mouth lo mouth lo matladukuntu evariki ayyiddi bro

[@RenzymEducation]

Couldn't get it. Is it Tamil language?

[@sindhujasindhu6337]

If your an Pakistan. How do u guess that it might be a tamil language

[@sindhujasindhu6337]

It's not tamil

[@unixux]

Omg bro can I buy you a mic ?

[@RenzymEducation]

Thanks. That would be great ;)

[@EugeneWilliamson-l6q]

Skye Manors

[@edmundhumenberger5255]

Please get a better microphone!!!!

[@kunchemanikanthaswamy1106]

Resonud occured

[@santoshsuggu4911]

I need professor number ,i want A2A class

[@Vilasmusical]

not a good explanation

[@RenzymEducation]

Thanks for your feedback. Did you dislike the general way of teaching, the material covered or some other technical issues like voice quality (which I know is not good)?