Verilog in 2 hours [English]

#verilog #asic #fpga
This tutorial provides an overview of the Verilog HDL (hardware description language) and its use in programmable logic design. We cover logic design process and then both synthesis constructs of Verilog as well as simulation constructs. We also discuss writing Verilog code for state machines. You will gain a basic understanding of Verilog enabling you to begin creating your designs. You can jump to relevant sections by clicking at time tags in the CONTENT below.
Slides and Solutions:
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CONTENT
(0:00) Course Overview
(1:34) PART I: REVIEW OF LOGIC DESIGN
(2:35) Gates
(4:24) Registers
(9:06) Multiplexer/Demultiplexer (Mux/Demux)
(10:16) Design Example: Register File
(13:56) Arithmetic components
(15:31) Design Example: Decrementer
(21:50) Design Example: Four Deep FIFO
(30:35) PART II: VERILOG FOR SYNTHESIS
(31:06) Verilog Modules
(37:20) Verilog code for Gates
(38:38) Verilog code for Multiplexer/Demultiplexer
(45:34) Verilog code for Registers
(48:11) Verilog code for Adder, Subtractor and Multiplier
(50:09) Declarations in Verilog, reg vs wire
(52:42) Verilog coding Example
(59:32) Arrays
(1:01:54) PART III: VERILOG FOR SIMULATION
(1:02:37) Verilog code for Testbench
(1:06:44) Generating clock in Verilog simulation (forever loop)
(1:08:31) Generating test signals (repeat loops, $display, $stop)
(1:16:06) Simulations Tools overview
(1:18:19) Verilog simulation using Icarus Verilog (iverilog)
(1:28:03) Verilog simulation using Xilinx Vivado
(1:37:02) PART IV: VERILOG SYNTHESIS USING XILINX VIVADO
(1:42:42) Design Example
(1:46:10) Vivado Project Demo
(1:49:49) Adding Constraint File
(1:54:25) Synthesizing design
(1:57:58) Programming FPGA and Demo
(2:00:31) Adding Board files
(2:01:44) PART V: STATE MACHINES USING VERILOG
(2:10:42) Verilog code for state machines
(2:17:22) One-Hot encoding

[@TusharKumar-iu4nt]

A really descriptive video on how to write verilog codes... Even a beginner like me was able to understand what lies in this intriguing topic in a single go!

[@faisalkashif2011]

A topic at the core of digital circuit design, covered by an expert of the field.

[@sridevia4819]

Thank you so much sir for this wonderful basic video which helps a lot for beginners like me

[@return2Quran]

Much needed short course. Thank you.

[@williesolomon614]

Very impressive tutorial. Thank you for sharing this to us..

[@1800haseeb]

Sir kindly give 1 session on VHDL as well like if we know Verilog how we can do programming in VHDL as well. I tried to understand it but its bit different and there are some differences which I am not able to understand in perspective of Verilog. Like this session if you can give VHDL session as well it will be great. Thank you so much

[@mdomarfaruque493]

You did an amazing job brother.Jazakallah

[@RenzymEducation]

Thanks a lot

[@MuhammadIrfan-ox4ud]

May I please get this ppt, for teaching purpose? Thanks a lot.

[@jaysingh6066]

paji tusi great ho, nice video. please make video in punjabi on Intel Altera FPGA also, thanks !!

[@RenzymEducation]

Meri punjabi koi inni changi nai

[@aleXelaMec]

Thanks for a great video. Was very useful for me!! If youll have more, it would be great. You are explaining very good. Maybe come more complex example. (In english)

[@RenzymEducation]

A little bit complex design example (in English) is that of a small processor
ruclips.net/video/HCzIK322Pzw/видео.html

[@aleXelaMec]

@@RenzymEducation too many steps ) but ill check. Thanks

[@sharathrajm7663]

A heartful thanks to ur work

[@ayrtontv6025]

Wow this was so helpful thank you so much

[@saidulsayem9193]

Thank You !!

[@RenzymEducation]

You're welcome!

[@kashifshah3183]

Excellent video

[@Adilamjad]

Good lecture!!

[@MCCreativeLegends]

Thank you so much 👏

[@thomasmccluskey2217]

Hi, thank you for the informative video! Would you be able to provide the entire code for the state machine please?

[@RenzymEducation]

I have added a Solutions folder with the slides link (tinyurl.com/verilog-slides ) that has FIFO and state machine code

[@thomasmccluskey2217]

@@RenzymEducation Thank you!

[@jsbadhon]

@@RenzymEducation sir this url is not working

[@RenzymEducation]

@@jsbadhon Try now

[@SMITPATEL-px7um]

hello ! can you please provide me reference code for amba ahb lite protocol for my research purposes thanks !

[@christonfredrick]

At 8:30 , when the enable signal is on the rising edge, the output shouldn’t 4 also be coming as output? Or does the output starts in the falling edge of the enable signal?

[@RenzymEducation]

Enable is probably drawn a bit wider on slide than it should have been. It was supposed to start rising after rising edge was passed and is sampled at next rising edge. That's why output starts at next rising edge.

[@christonfredrick]

@@RenzymEducation Thanks for the clarification!

[@marwanal-yoonus280]

Dear Sir
Thank you very much for this helpful video
Please, I try to write the following Verilog code in Vivado, the synthesis process is OK but when I want to implement it an error signal appear !!
module Tog_not (hsync, EOL, q);
input hsync, EOL;
output reg q;
always @ (posedge hsync)
begin
q

[@snezestudiesandbeauties5815]

You are not mention clk as a input

[@marwanal-yoonus280]

@@snezestudiesandbeauties5815 Thank you very much for your answer.

[@joecox9958]

your sound echo not very clear, do you use speaker phone?

[@RenzymEducation]

It was recorded using laptop's mic during covid days

[@animeshsrivastava5067]

Please can you design a course on System Verilog and verification through it via UVM? It's not available fully anywhere and may help us a lot.

[@RenzymEducation]

It might take a while as I haven't used system verilog

[@animeshsrivastava5067]

@@RenzymEducation Thank you so much for the reply. Additionally, please can I request for verification through Verilog videos. In general, the linear test benches are not considered for complicated circuits and other TBs are also present. It'll be great if you can guide on this topic.

[@kunchemanikanthaswamy1106]

Voice clarty is not good

[@oats7924]

Okay but how do you download verilog? Where does it take place?

[@RenzymEducation]

There is a link to install iverilog (its also there in video description)
ruclips.net/video/Y0bNVStZok4/видео.html

[@vikramadityatechchannel8118]

sir do you have sdr transmitter code

[@PC-pw7hv]

If you got SDR code. pls share

[@user-qu4kl4du6z]

India?

[@RenzymEducation]

Pakistan

[@editz3420]

Bro mouth lo mouth lo matladukuntu evariki ayyiddi bro

[@RenzymEducation]

Couldn't get it. Is it Tamil language?

[@sindhujasindhu6337]

If your an Pakistan. How do u guess that it might be a tamil language

[@sindhujasindhu6337]

It's not tamil

[@unixux]

Omg bro can I buy you a mic ?

[@RenzymEducation]

Thanks. That would be great ;)

[@kunchemanikanthaswamy1106]

Resonud occured

[@edmundhumenberger5255]

Please get a better microphone!!!!

[@santoshsuggu4911]

I need professor number ,i want A2A class

[@Vilasmusical]

not a good explanation

[@RenzymEducation]

Thanks for your feedback. Did you dislike the general way of teaching, the material covered or some other technical issues like voice quality (which I know is not good)?