Design Integration: Substrate Design Optimization for Chiplet Architecture

Road to Chiplets - Design Integration
Substrate Design Optimization for Chiplet Architecture
Deepak Kulkarni
AMD
The advent of smart devices, artificial intelligence and 5G is driving an explosion in demand for high performance computing (HPC). With the slowdown in Moore’s law, chiplet architecture is critical to sustain the rapid growth in HPC. In this talk, we will discuss the critical role of substrates and the need for design co-optimization at every stage of the product life cycle. We introduce machine learning based tools that are trained to estimate the impact of design on yield, cost, and capacity. We conclude with the benefits of these analytics tools and road ahead for advanced packaging.