System Verilog Testbench code for Full Adder | VLSI Design Verification Fresher

[@ExploreElectronicsPlus]

Contents :
0:00 Introduction
0:25 Full adder Design Code
2:13 Testbench Architecture
5:01 TB Top
6:30 Interface
7:25 Transaction Class
9:17 Generator Class
12:48 Driver Class
16:42 Monitor Class
19:66 scoreboard class
23:00 Environment class
25:26 Test Class

[@anjanianjii1154]

sir the way u thought is very nice and easily understandable for basic learners sir

[@renukatali919]

Very nicely presented sir, tell us about eda tool , how to use it
Handle means what, how to understand it

[@Venu_gopal29]

thank you🙏, sir very clear explanation👌,pls do any other one with clocking block and modport.

[@ExploreElectronicsPlus]

Sure Will do it next. Keep following

[@ExploreElectronicsPlus]

Hope you share and recommend to friends

[@anjinin5602]

Very understable make one example for sequential circuit

[@ExploreElectronicsPlus]

@@anjinin5602 check video on D Flipflop with uvm testbench

[@explainit-k14]

which method of mailbox handle passing is more used in the industry
1. one which you did in the code, passing handle in function new
2. in common and then calling it through scope resolution ( :: ). (my preference but can switch to first)

[@nithishkanna7]

can you please make a video for sequential circuit like d flip flop in future,sir?

[@ExploreElectronicsPlus]

@@nithishkanna7 check DFlipflop UVM testbench is explained in other video

[@nithishkanna7]

@@ExploreElectronicsPlus is it necessary to include the module in the order in environment just as same as the order we created

[@ExploreElectronicsPlus]

@@nithishkanna7 yes, use order or naming connections

[@nithishkanna7]

sir, even though i followed the instructions and write the code in eda playground, but still i had an error in mailbox in every block and generates "'ERROR VCP2000 "Syntax error. Unexpected token: transaction[_IDENTIFIER]." "generator.sv" 3 14", so what should i do ?
class generator;
transaction trans;
mailbox gen2dr;
function new(mailbox gen2dr);
this.gen2dr=gen2dr;
endfunction

task main();
repeat(2) begin

trans =new();
trans.randomize();

gen2dr.put(trans);
trans.display("generator class signals");
end

endtask
endclass

[@ExploreElectronicsPlus]

@@nithishkanna7 can you share your eda proj link here or dm in Instagram

[@nithishkanna7]

@@ExploreElectronicsPlus sir I'm so grateful for your help

[@BhupathiRaviteja]

👏👏👏👏

[@crazyzone4064]

Hi sir! Is this playground eda open source? Can we practice in it freely?

[@ExploreElectronicsPlus]

yes it is free. you can sign up and use it freely

[@crazyzone4064]

@@ExploreElectronicsPlus TQ

[@crazyzone4064]

@@ExploreElectronicsPlus sir one doubt in Cadence tool or in vivado we just wrote one testbench program but why here we are writing so many 😅😅 iam new don't have much idea...m

[@ExploreElectronicsPlus]

@@crazyzone4064 verilog testbench can be written for small designs.
For bigger designs, we need to check many scenarios and many aspects of verification. Verilog Testbench does not cover all those. So in Industry standard methodology is used. (It's a big question and we need to understand this with the exact answer. I will try to answer you in a video on this)

[@crazyzone4064]

@@ExploreElectronicsPlus it would be great help if u do that 🙏🙏