Verification of combinational adder using sv-uvm

[@venkateshiyer5073]

thank you so much for explaining. for a simple adder, to have a verif environment i feel it requires lot of code & components to verify

[@faizangokak3355]

In uvm_sequnce, in the task body, we can make use of `uvm_do(); macro right? Which will perform request response from sequence to driver. Like
Class...........
seq_item req; //handler
task body();
`uvm_do(req);
end task
endclass
can we pass the handler of the seq item in the do macro? Instead, it writes more steps. We can reduce it r, right?

[@MunsifMAhmad]

Yes...

[@vamshidharreddy33]

can you make videos on protocols please

[@MunsifMAhmad]

Will try..

[@ZakirHussain12345]

sir can you please make video on ALU verification using cocotb

[@MunsifMAhmad]

Not sure about cocotb but with pyuvm will try in coming future, if possible then with cocotb also..

[@faizangokak3355]

How to drive the value directly from the driver, without randomization in sequence_item?

[@MunsifMAhmad]

You can give hard coded value in the driver directly.

[@faizangokak3355]

@@MunsifMAhmad Yeah, that variable must be declared in the sequence item also Is it?

[@MunsifMAhmad]

@@faizangokak3355
Yes..