In uvm_sequnce, in the task body, we can make use of `uvm_do(); macro right? Which will perform request response from sequence to driver. Like Class........... seq_item req; //handler task body(); `uvm_do(req); end task endclass can we pass the handler of the seq item in the do macro? Instead, it writes more steps. We can reduce it r, right?
thank you so much for explaining. for a simple adder, to have a verif environment i feel it requires lot of code & components to verify
In uvm_sequnce, in the task body, we can make use of `uvm_do(); macro right? Which will perform request response from sequence to driver. Like
Class...........
seq_item req; //handler
task body();
`uvm_do(req);
end task
endclass
can we pass the handler of the seq item in the do macro? Instead, it writes more steps. We can reduce it r, right?
Yes...
can you make videos on protocols please
Will try..
sir can you please make video on ALU verification using cocotb
Not sure about cocotb but with pyuvm will try in coming future, if possible then with cocotb also..
How to drive the value directly from the driver, without randomization in sequence_item?
You can give hard coded value in the driver directly.
@@MunsifMAhmad Yeah, that variable must be declared in the sequence item also Is it?
@@faizangokak3355
Yes..