Nice explanation, but let me also slightly critisize one aspect. In your diagram the DATA and VALID signals are switching right *before* the clock's rising edge. In reality all flip-flops driven by the particular clock would switch right *after* the clock's rising edge. Same is true for the READY signal which you show switching simultaneously with the CLK. The READY signal is the same as DATA and VALID in the sense that it is a Q-output of a flip-flop, tacted by the CLK. So the READY signal will naturally switch simultaneously with DATA and VALID right *after* the CLK rising edge.
Alas, you're right. Originally I recorded this for another student, and the (bizarre) way we were running simulations had the testbench stimulus only getting applied just in time for the clock edge, so this video is kind of misleading for everyone else. Thanks for pointing this out! P.S. I'm shocked how many people have found this video, had I known I would have tried to do a better job...
I'm glad you asked :-) What I described in the video was the basic handshaking idea used in AXI Stream. The "ready to send + ready to receive" idiom is very widely used, and you are right that it is quite loosely defined. For example, many handshaking implementations use active-low polarity for tready (and call it "pause" or something). The actual protocol has much more to it, and you would use it to ensure compatibility with others' designs. Here are some extra features that are specific to the AXI Stream protocol: - (very important) on the sender side, tvalid may NOT depend on tready, though the receiver is allowed to make tready depend on tvalid. This prevents combinational loops - standardized polarity of tready and tvalid. No need to remember to add NOT gates all over the place - well-defined (optional) extensions. In the video I mentioned tlast, but there are a few others, such as tkeep, which is a byte-enable signal for partial writes. In my experience, it's actually a pain to support the optional parts, but it helps a lot that they are standard. I can only imagine the suffering if each IP used a different idea to denote (for example) packet boundaries.
What is the difference between AXI memory mapped and AXI stream then? I think memory mapped also works same way as you explained in AXI stream. Not able to understand the difference.
That is very kind! At the moment this is literally my only tutorial video, so a donation button doesn't seem worth the trouble. But maybe I'll make more tutorials (any requests?)
Perhaps a comparison of different AMBA protocols, and when it's appropriate to use each one. Maybe with some practical examples too 😋 nice work so far!
pretty good, clear enough in oral but you can do more practices on presentations to boost more viewer's coming to your channel. By more interact with viewers, you can do better.
![The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]](http://i.ytimg.com/vi/Ko3wmIVsOtM/mqdefault.jpg)
![The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]](/img/tr.png)
![I.N "HALLUCINATION" | [Stray Kids : SKZ-PLAYER]](http://i.ytimg.com/vi/n5B5q1Hwt_U/mqdefault.jpg)
very good! you`re the master on Paint too!
This tutorial is definitely not crappy. Whish you would do more Zynq related basic stuff in exactly this manor. Greetings
I've thought about making more videos. Any specific requests?
@@biquinary let's say AXI Video Stream?
@@biquinary but for future videos I can recommend something like OneNote or xournal++
Great video, almost feels like you are studying AXI stream besides a water stream.
Please continue your video &axi protocol explanation still testbench..... :)
Loved the tutorial, definitely not crappy
Nice explanation, but let me also slightly critisize one aspect. In your diagram the DATA and VALID signals are switching right *before* the clock's rising edge. In reality all flip-flops driven by the particular clock would switch right *after* the clock's rising edge. Same is true for the READY signal which you show switching simultaneously with the CLK. The READY signal is the same as DATA and VALID in the sense that it is a Q-output of a flip-flop, tacted by the CLK. So the READY signal will naturally switch simultaneously with DATA and VALID right *after* the CLK rising edge.
Alas, you're right. Originally I recorded this for another student, and the (bizarre) way we were running simulations had the testbench stimulus only getting applied just in time for the clock edge, so this video is kind of misleading for everyone else. Thanks for pointing this out!
P.S. I'm shocked how many people have found this video, had I known I would have tried to do a better job...
When would one use this instead of something like XGMII? This seems like a very general purpose, loosely designed protocol.
I'm glad you asked :-)
What I described in the video was the basic handshaking idea used in AXI Stream. The "ready to send + ready to receive" idiom is very widely used, and you are right that it is quite loosely defined. For example, many handshaking implementations use active-low polarity for tready (and call it "pause" or something).
The actual protocol has much more to it, and you would use it to ensure compatibility with others' designs. Here are some extra features that are specific to the AXI Stream protocol:
- (very important) on the sender side, tvalid may NOT depend on tready, though the receiver is allowed to make tready depend on tvalid. This prevents combinational loops
- standardized polarity of tready and tvalid. No need to remember to add NOT gates all over the place
- well-defined (optional) extensions. In the video I mentioned tlast, but there are a few others, such as tkeep, which is a byte-enable signal for partial writes. In my experience, it's actually a pain to support the optional parts, but it helps a lot that they are standard. I can only imagine the suffering if each IP used a different idea to denote (for example) packet boundaries.
@@biquinary That makes a tonne of sense. Thanks for providing this stellar content!
What is the difference between AXI memory mapped and AXI stream then? I think memory mapped also works same way as you explained in AXI stream. Not able to understand the difference.
Donation button anywhere?
That is very kind! At the moment this is literally my only tutorial video, so a donation button doesn't seem worth the trouble. But maybe I'll make more tutorials (any requests?)
Perhaps a comparison of different AMBA protocols, and when it's appropriate to use each one. Maybe with some practical examples too 😋 nice work so far!
NIce tutorial, thanks a lot!
sorry..axi stream has different signals right like TDATA, TVALID.. . this seems like AXI4/3
pretty good, clear enough in oral but you can do more practices on presentations to boost more viewer's coming to your channel. By more interact with viewers, you can do better.
It is true for APB but not for AXI
Damn a lot of views on this