- Видео 87
- Просмотров 21 143
biquinary
Добавлен 24 дек 2010
I record myself doing projects because for some reason it helps me make progress. I don't expect or even really want people to watch. idk
English dub of "Le mirage de la voiture électrique" (The False Promises of Electric Cars)
English dub of "Le mirage de la voiture électrique" (The False Promises of Electric Cars)
Просмотров: 43
Видео
How to use the fake FPGA on home Linux computers
Просмотров 1934 года назад
How to use the fake FPGA on home Linux computers
How to use the fake_fpga on ECF comuters
Просмотров 9824 года назад
How to use the fake_fpga on ECF comuters
Using the fake FPGA on a home Windows computer
Просмотров 1,2 тыс.4 года назад
Using the fake FPGA on a home Windows computer
Using the DE1 simulator on DESL computers
Просмотров 3354 года назад
Using the DE1 simulator on DESL computers
Debug Governor Demo (For my Master's project)
Просмотров 664 года назад
Debug Governor Demo (For my Master's project)
Please continue your video &axi protocol explanation still testbench..... :)
Mort Garson has entered the chat
sorry..axi stream has different signals right like TDATA, TVALID.. . this seems like AXI4/3
Loved the tutorial, definitely not crappy
😈 "PromoSM"
very good! you`re the master on Paint too!
Great video, almost feels like you are studying AXI stream besides a water stream.
Went to go check something in the recording... and oops my mic wasn't working that whole time. Oh well.
Good , Thanks for your effort
Nice explanation, but let me also slightly critisize one aspect. In your diagram the DATA and VALID signals are switching right *before* the clock's rising edge. In reality all flip-flops driven by the particular clock would switch right *after* the clock's rising edge. Same is true for the READY signal which you show switching simultaneously with the CLK. The READY signal is the same as DATA and VALID in the sense that it is a Q-output of a flip-flop, tacted by the CLK. So the READY signal will naturally switch simultaneously with DATA and VALID right *after* the CLK rising edge.
Alas, you're right. Originally I recorded this for another student, and the (bizarre) way we were running simulations had the testbench stimulus only getting applied just in time for the clock edge, so this video is kind of misleading for everyone else. Thanks for pointing this out! P.S. I'm shocked how many people have found this video, had I known I would have tried to do a better job...
Hey! This seems super interesting! You wouldn't have a recording of the first session with the audio intact? That would be even better :)
No, sorry, I goofed up my OBS and the audio is gone for good.
@@biquinary no worries! Still looks like very valuable content, there's not that much advanced pico8 content out there :)
What is the difference between AXI memory mapped and AXI stream then? I think memory mapped also works same way as you explained in AXI stream. Not able to understand the difference.
Thanks for translating. I'm a fan of public transportation.
It is true for APB but not for AXI
Damn a lot of views on this
finally some good content
I'll send you an invoice
When would one use this instead of something like XGMII? This seems like a very general purpose, loosely designed protocol.
I'm glad you asked :-) What I described in the video was the basic handshaking idea used in AXI Stream. The "ready to send + ready to receive" idiom is very widely used, and you are right that it is quite loosely defined. For example, many handshaking implementations use active-low polarity for tready (and call it "pause" or something). The actual protocol has much more to it, and you would use it to ensure compatibility with others' designs. Here are some extra features that are specific to the AXI Stream protocol: - (very important) on the sender side, tvalid may NOT depend on tready, though the receiver is allowed to make tready depend on tvalid. This prevents combinational loops - standardized polarity of tready and tvalid. No need to remember to add NOT gates all over the place - well-defined (optional) extensions. In the video I mentioned tlast, but there are a few others, such as tkeep, which is a byte-enable signal for partial writes. In my experience, it's actually a pain to support the optional parts, but it helps a lot that they are standard. I can only imagine the suffering if each IP used a different idea to denote (for example) packet boundaries.
@@biquinary That makes a tonne of sense. Thanks for providing this stellar content!
pretty good, clear enough in oral but you can do more practices on presentations to boost more viewer's coming to your channel. By more interact with viewers, you can do better.
Donation button anywhere?
That is very kind! At the moment this is literally my only tutorial video, so a donation button doesn't seem worth the trouble. But maybe I'll make more tutorials (any requests?)
Perhaps a comparison of different AMBA protocols, and when it's appropriate to use each one. Maybe with some practical examples too 😋 nice work so far!
This tutorial is definitely not crappy. Whish you would do more Zynq related basic stuff in exactly this manor. Greetings
I've thought about making more videos. Any specific requests?
@@biquinary let's say AXI Video Stream?
@@biquinary but for future videos I can recommend something like OneNote or xournal++
NIce tutorial, thanks a lot!
Good job!! Im realy interesting in this project.
Since this demo, we'e managed to make this work at 100G. Check out our FCCM paper: www.fccm.org/past/2020/proceedings/2020/pdfs/FCCM2020-65FOvhMqzyMYm99lfeVKyl/580300a047/580300a047.pdf
Huh interesting. When are you going to simulate the universe?
I totally understand everything you were doing haha
I be coding