This is the sponsored readout. I am hoping for an Ian video to answer some questions and comparisons that come up: Is it possible to compare some of the technologies Intel talks about directly to those mentioned by TSMC? For example power rail sounds like power via for backside power delivery?
This is such an interesting / odd video. What is the target audience of this kind of video? Does TSMC have difficulty of finding customers? Does TSMC need to inform end consumers about their services / products? I love this video, I really do! This video is just so... cool! Well done for getting another TSMC sponsorship! But I genuinely am interested in the questions I asked above. :)
Mind share/message amplification. But also Intel's doing significant work to promote their offering, and they don't want Intel to be the only message in the room.
Brand marketing is pretty important, even for well-established brands. Several dozen million people turn 16 (18, 24...) each week in the world and a decent sliver of them will start seeing press releases from consumer products companies which mention these fabs.
Wow after knowing Intel would separate power and signal delivery between the back side and front side of the silicon wafer, TSMC is also revealing their plans to do it too! Also it's interesting that TSMC is using nano sheets for their A16 while Intel plans to use nano Ribbon for A18. It's all coming together like crabs.
Intel using nanosheets with their 20A node, which is in fab now and releasing products later this year. 20A also has backside power. So Intel is ahead.
Huh... You know, I didn't expect for TSMC to be talking about angstrom chips already but here we are. I guess that something in the market spooked them to do that, as much as I would like to think that it is IFS... I am not sure it is.
You don't need to be spooked by anyone, when your next gen product is the last of nm nomenclature, and there is a logical question: what is next? It is not like Intel is chatting about products planned 20 years from now, while their current product is struggling.
ASML’s CTO said in a recent Dutch interview that they are actually not below nm scale yet, that’s just marketing. High NA is somewhere below 10 nm. Previous gen at about 10 nm. Also, he said they finally got a proof of concept working on High NA so "it is now very unlikely to go wrong” while it has been very uncertain so far (as it always is with a new machine he said)
@Tuckerslam the newest chips 🍟 are actually manufactured on 32nm process ? I didn't even think about what the actual nm process is since the chip companies started lying to make the marketing seem more impressive
@@cryptocsguy9282 The math behind is pretty simple: they now stack a 32 nm transistor below other 32 nm transistor and proclaim overall density to be twice higher, or thrice if they manage three floors like that, and so on. That's what FinFET was about, and whatever came after it.
Wow! SoW is pretty interesting. I had joked back when Apple introduced the M1 Ultra that they might go data center stitching four M2 Max dies together to scale it out. LOL! Great stuff, Ian! Thanks for keeping us all informed.
@nextcurve similar but less advanced semiconductor manufacturing techniques already allowed for turning an entire silicon wafer into 1 computer chip in a process called wafer scake integration as far back as the 1980s but it never took off then. There's an AI company called Cerebras that makes AI computers using the wafer scale integration technique but idk if it's TSMC's SoW
@@cryptocsguy9282 yes, I know about them. They make what is essentially a massive NPU. My take is that SoW is like having a massive M4 Plaid or M4 Ridiculous.
@@nextcurve yes according to their own metrics Cerebras AI offerings are better than Nvidia because of more parallelism happening in one giant chip while Nvidia GPUs need to be linked up to each other so it's a bit slower but the Nvidia brand has way more hype & consumer recognition.
@@cryptocsguy9282 like Ian alludes to, Jensen sees the writing on the wall. He also needs to go wafer scale. It’s the best avenue to continue scaling and densifying his systems. Water cooling, data type will largely be tapped out when NVL 72 ships.
I'm all about that backside power. Aka Badonkadonk. Intel calls it PowerVia. I don't know why they don't work with motherboard managers to allow for backside cooling. Put all the VRMs on the back close to the chip to keep voltage as stable as possible and put all the memory on the frontside as close to the chip to keep latency down and have coolers on both sides of the board.
Selectively Optimizing transistors for power trade offs seems like a good fit with wafer scale products … heat dissipation has got to be a big issue. I always considered the heat build up issue would push wafer scale designs into long narrow wafer slices. This allows the heat buildup to dissipate more effectively than from a square wafer chunk.
It appears to me that Intel, for the first time in many years, is ahead of TSMC! For decades TSMC was the fast follower, then TSMC leaped ahead of Intel due to Intel's strategic mistake of not embracing EUV early enough. Now that Intel has EUV, they have quickly caught up and it appears they have even surpassed TSMC. Intel 20A node, which is essentially out now, already has gate all around transistors (nanosheet, ribbonFET, whatever you wanna call it). 20A also already is using backside power delivery. So Intel already has two new key technologies built into ththeir 20A node! Intel 18A will be out just a bit after 20A in late 2024, and will put Intel even further ahead. It appears, Intel will also stay ahead thru the remainder of the decade. Here's why. Intel is the only foundry to have purchased, installed, and begun using an ASML high NA EUV stepper. These can create features 1.66x smaller than the standard NA EUV stepper. TSMC has arrogantly said they don't need hight NA until 2030. Sound familar? This sounds just like Intel did circa 2017, when they said they didn;t need EUV. Can TMSC eek out something competitive without it? Probably, but they will have to rely on mulitpatterning and lower yields. Intel 14A will be out in 2026, likely one year ahead of TSMC's A16. Not only will 14A be out a year earlier, it is almost guaranteed to be better since it uses high NA. Intel is back. WIll their foundry be as big, no. Will it immediately win over Apple and Nvidia? No, but it will eventually. I think many companies that demand to be on leading edge, will make the switch in 2026 with Intel 14A
How is it called "angstrom"! when it's 1.6nm or in the case of Intel, 1.8nm or 1.4nm!? shouldn't it be in the sub-nano realm, in order to be called angstrom (100 picometers)!?
TSMC also said that high NA litho isnt important right now and will keep using just EUV and not use high NA EUV for awhile...while Intel is jumping to high NA EUV ASAP. thats a wrong move by TSMC as thats what Intel said before too, and thats how Intel fail behind from TSMC and Samsung.
Not impressed. TSMC hit speed bumps with N3 and is slowing down. On the other hand now that Intel has turned their ship around they are going as fast as possible to surpass or match TSMC. Apple is dealing with the effects of TSMC hitting a wall, as their M silicon continues to grow in area gen after gen after gen as density gains are getting anemic.
dude, Intel is going to release 3 2nm products this year and another 3 next year. they'll reach 18A and 14A before TSCM does 16A, the machines that make sub 2nm possible have all be bought by intel, which will make TSCM at least 6 months behind, if not more.
@@MaxIronsThirdIntel MTL & ARL CPUs use TSMC for 3 of the 4 Tiles. Intel’s Gaudi 3 AI GPU uses TSMC 5nm exclusively. Wake me up when Intel actually uses its own foundry.
Hey Dr Cuttess, if you want to improve your chroma keying, the key (heh) is to use more lights. The more/bigger the better. If you are filming with a camera that let's you film in raw or raw-like, or something like Sony's S-Log with high dynamic range, you can in post tone down the lighting so it looks natural. However, by having that much lighting, the camera picks up the color differences much better and the surfaces are lit in a more homogenous way, so the cutoff of your silhouette gets much sharper and not jittery. In general, the more you can lower the ISO, the better, since a lower ISO means the camera does less guessing and colors are closer to real life. High ISO also introduces jitter and noise (bad for keying).
Good to know! It's already better than it used to be. One of my issues is that my office is only 12ft x 10ft - and most of that is storage for hardware. Leaves the area to film in very small
@@TechTechPotato yeah, that definitely complicates things. If there’s only one thing you can focus on, let it be having a uniform and strong lighting. Uniform as in lighting from various angles, so that there are no areas in shade confusing the camera/editor. Also prefer less but bigger lights to more but smaller lights, since for the same lumens, the bigger the source, the softer the shadows.
So TSMC is following Intel with the angstrom designation and Intel and TSMC both have pretty cool tech coming in the latter half of the decade... What's Samsung doing?
And I can't wait for progress of photonics, because IMHO it is what is next after silicon. Because with less power, it mean it can easily go 3D, and we don't talk about squares but cubics of compute.
I think (but I could be wrong) TSMC said something on the line "extreme UV is not required for sub 2nm nodes", so perhaps they don't need them, but it would be a bit strange that Intel spent so much money to book and buy the first 6 ASML machines if they were not essential. Or maybe TSMC is confident that this SPR can bring them to a node that matches intel's 18A, but without those machines
Hi, I’m not technical, but this one side for signalling and other side for power delivery, is it broadly similar to what Intel cals as backside power delivery that they are probably going to implement with PowerVia?
Tall and short standard cell libraries are pretty common at larger scales in my experience. Was it less common at these deep scales due to patterning requirements forcing very regular structures?
Initially thought tsmc made an improved a16 bionic. Then came to know it was Angstrom. Been a long time, I heard angstrom unit in my physics lecture. 😂
Dr. Cultress, u need to grab one of those "Guai Guai" (乖乖) coconut-flavored edible chips from TSMC! That will be so funny eating them on air! Since TSMC engineers aren't allowed to eat nor film them inside the fab. :D
Well summarized what we can expect in the future with chip manufacturing overall besides what to expect from the industry leader TSMC. A16, more advanced MCM packaging and of course silicon photonics make all sense to be essential in the future.
The financing Intel (and others} is receiving from the federal government - is it non recourse - a grant - what might be the basic terms involved? Wondering }
It's in the description, and on screen in the first few seconds. It's also part of the hashtags. Meets all UK OFCOM requirements, which are stricter than US FTC.
Props to you. I understand that getting text on top of the video is another step of work. I guess you could consider it anyhow. As you can always be excellent and not just passing the bar. Put your priorities where they matter to you and focus on being consistent whether you put disclaimers on screen. Inconsistency would be much worse as that will generate new conspiracies so i understand where you are coming from.
Good presentation,tsmc aiming 3D solution by stack up nano sheet aka cfet while Intel is trying High NA EUV to max the density in 2D way,will see who wins the battle
Oh sorry, I thought you were talking about bspdn with gaa. Yes I've read the Intel research on variable width ribbons, but they've not made an effort to codify it as an offering publicly.
![[36] TSMC Technology Interview: A16 Node, System-on-Wafer, and High-NA](http://i.ytimg.com/vi/WgJnzygxBk0/mqdefault.jpg)
Blimey, how on earth did you manage to get sponsorship from TSMC?
We did one last year :)
Also my first thought ❤
Probably Nepotism.
Solid shill track record and staying away from the usual corporate drama, ie. being an informative good boy.
@@ZeZeBatata69 does anyone else do it better ?
Gawd damn. TSMC sponsorship is wild
This is the sponsored readout.
I am hoping for an Ian video to answer some questions and comparisons that come up: Is it possible to compare some of the technologies Intel talks about directly to those mentioned by TSMC?
For example power rail sounds like power via for backside power delivery?
Yup, similar thing, different marketing name
This is such an interesting / odd video. What is the target audience of this kind of video? Does TSMC have difficulty of finding customers? Does TSMC need to inform end consumers about their services / products?
I love this video, I really do! This video is just so... cool! Well done for getting another TSMC sponsorship! But I genuinely am interested in the questions I asked above. :)
Mind share/message amplification. But also Intel's doing significant work to promote their offering, and they don't want Intel to be the only message in the room.
I see, that's cool!
Have you ever tried a sponsorship from Arm? It is British, right?
Brand marketing is pretty important, even for well-established brands. Several dozen million people turn 16 (18, 24...) each week in the world and a decent sliver of them will start seeing press releases from consumer products companies which mention these fabs.
TSMC’s advanced packaging fab is in our childhood hometown…
Wow after knowing Intel would separate power and signal delivery between the back side and front side of the silicon wafer, TSMC is also revealing their plans to do it too! Also it's interesting that TSMC is using nano sheets for their A16 while Intel plans to use nano Ribbon for A18. It's all coming together like crabs.
Intel using nanosheets with their 20A node, which is in fab now and releasing products later this year. 20A also has backside power. So Intel is ahead.
@@sofiabonetti. We'll see if these even make it out the fabs before rusting
Huh... You know, I didn't expect for TSMC to be talking about angstrom chips already but here we are. I guess that something in the market spooked them to do that, as much as I would like to think that it is IFS... I am not sure it is.
You don't need to be spooked by anyone, when your next gen product is the last of nm nomenclature, and there is a logical question: what is next? It is not like Intel is chatting about products planned 20 years from now, while their current product is struggling.
ASML’s CTO said in a recent Dutch interview that they are actually not below nm scale yet, that’s just marketing. High NA is somewhere below 10 nm. Previous gen at about 10 nm. Also, he said they finally got a proof of concept working on High NA so "it is now very unlikely to go wrong” while it has been very uncertain so far (as it always is with a new machine he said)
@@C4rb0neum Meh. It's still same old 32nm, for everybody, just in layers with fancy titles dreamt up by marketing clowns.
@Tuckerslam the newest chips 🍟 are actually manufactured on 32nm process ? I didn't even think about what the actual nm process is since the chip companies started lying to make the marketing seem more impressive
@@cryptocsguy9282 The math behind is pretty simple: they now stack a 32 nm transistor below other 32 nm transistor and proclaim overall density to be twice higher, or thrice if they manage three floors like that, and so on. That's what FinFET was about, and whatever came after it.
Wow! SoW is pretty interesting. I had joked back when Apple introduced the M1 Ultra that they might go data center stitching four M2 Max dies together to scale it out. LOL! Great stuff, Ian! Thanks for keeping us all informed.
@nextcurve similar but less advanced semiconductor manufacturing techniques already allowed for turning an entire silicon wafer into 1 computer chip in a process called wafer scake integration as far back as the 1980s but it never took off then. There's an AI company called Cerebras that makes AI computers using the wafer scale integration technique but idk if it's TSMC's SoW
@@cryptocsguy9282 yes, I know about them. They make what is essentially a massive NPU. My take is that SoW is like having a massive M4 Plaid or M4 Ridiculous.
@@nextcurve yes according to their own metrics Cerebras AI offerings are better than Nvidia because of more parallelism happening in one giant chip while Nvidia GPUs need to be linked up to each other so it's a bit slower but the Nvidia brand has way more hype & consumer recognition.
@@cryptocsguy9282 like Ian alludes to, Jensen sees the writing on the wall. He also needs to go wafer scale. It’s the best avenue to continue scaling and densifying his systems. Water cooling, data type will largely be tapped out when NVL 72 ships.
I'm all about that backside power. Aka Badonkadonk. Intel calls it PowerVia. I don't know why they don't work with motherboard managers to allow for backside cooling. Put all the VRMs on the back close to the chip to keep voltage as stable as possible and put all the memory on the frontside as close to the chip to keep latency down and have coolers on both sides of the board.
@kahnzo that's something Apple could do. I x86 PC market has no vertical integration so ai guess manufacturs just don't care
@@cryptocsguy9282 But Intel and AMD still design the CPU socket. They decide what size it is, what it includes, keep-out zones, etc.
System on wafer is extremely cool
I thought Brits called them crisps 🤔
If 1.6 nm doesnt mean the gate length then what does it actually mean how was the name taken ?
It's merely an extrapolation of what gate length you would need to reach these densities with planar transistors.
Ohh okk thankss
Sounds exciting 😀 😮 seeing 👀 what comes after 2nm🍟 chip designs especially photonics & 3D stacked transistors.
Kind of beats the point of checking your channel if you are going to repeat their press release.
One important detail: will this be achieved with the present state of the art EUV lithography, or is there an announcement by ASML also in the cards?
Selectively Optimizing transistors for power trade offs seems like a good fit with wafer scale products … heat dissipation has got to be a big issue. I always considered the heat build up issue would push wafer scale designs into long narrow wafer slices. This allows the heat buildup to dissipate more effectively than from a square wafer chunk.
It’s a huge amount of innovation.. but only a 20% density increase going from N3 to A16….
3:20 How do you think Intel produced Core gen 12/13/14 CPUs with P-cores and E-cores?
Is "System On Wafer" , for AI Supercomputers a whole new business segment? What do you think about the economical impact of this?
Limited outside a select few.
I like fat chunky chips not thin ones and gin is best for tonics!
SPR is not what intel just announced as thru silicon vias?
nope, it's coming with 18A. 2025
@@TechTechPotato A yes the size matters
How does this differ from Intel's backside power delivery? They sound like similar concepts
It's probably work 😆
@@diamondlion47Yep the main differnce is TSMC's tech will work while Intel will be trying to make It work for years and then skip It 🤣
So leaving AnandTech was the best decision you made. Anand never got sponsorship from TSMC even after TWENTY years. That _is_ HUGE.
Meanwhile me designing IP on N28 ;_;
WOW! Big corporation announces [things are fine news]! Did they just announced [thing that reassures shareholders]? Omg, they totally did! Wow.
It appears to me that Intel, for the first time in many years, is ahead of TSMC! For decades TSMC was the fast follower, then TSMC leaped ahead of Intel due to Intel's strategic mistake of not embracing EUV early enough. Now that Intel has EUV, they have quickly caught up and it appears they have even surpassed TSMC. Intel 20A node, which is essentially out now, already has gate all around transistors (nanosheet, ribbonFET, whatever you wanna call it). 20A also already is using backside power delivery. So Intel already has two new key technologies built into ththeir 20A node! Intel 18A will be out just a bit after 20A in late 2024, and will put Intel even further ahead. It appears, Intel will also stay ahead thru the remainder of the decade. Here's why. Intel is the only foundry to have purchased, installed, and begun using an ASML high NA EUV stepper. These can create features 1.66x smaller than the standard NA EUV stepper. TSMC has arrogantly said they don't need hight NA until 2030. Sound familar? This sounds just like Intel did circa 2017, when they said they didn;t need EUV. Can TMSC eek out something competitive without it? Probably, but they will have to rely on mulitpatterning and lower yields. Intel 14A will be out in 2026, likely one year ahead of TSMC's A16. Not only will 14A be out a year earlier, it is almost guaranteed to be better since it uses high NA. Intel is back. WIll their foundry be as big, no. Will it immediately win over Apple and Nvidia? No, but it will eventually. I think many companies that demand to be on leading edge, will make the switch in 2026 with Intel 14A
You have been too fast in your conlusions. Doesn't matter what tech Intel has If A LOT of their last CPUs have defects...
The whole video sounds like TechTechPotato has become the Marketing Intern at TSMC
300mm chip? How could you be supposed to cool that chip?
300mm waffer not 300 mm chips a 300 mm chip = 17.3mm^2
@@lasarith2At 4:45 in the video, they do indeed speak of wafer-sized solutions for AI applications.
The wafer will be mounted to 100kg copper radiator, and cooled with jet engine fan
How is it called "angstrom"! when it's 1.6nm or in the case of Intel, 1.8nm or 1.4nm!? shouldn't it be in the sub-nano realm, in order to be called angstrom (100 picometers)!?
angström is 10^-10 and nano is 10^-9 so 10 angström are 1 nano. Angström does not follow the typical scale
bc micrometer and milimeter are too similar when abreviated, you gotta remember that these are all marketing terms at this point.
TSMC also said that high NA litho isnt important right now and will keep using just EUV and not use high NA EUV for awhile...while Intel is jumping to high NA EUV ASAP. thats a wrong move by TSMC as thats what Intel said before too, and thats how Intel fail behind from TSMC and Samsung.
So 3nm > 16A no mention of 2nm or 18A 🤔
Xi will want this new tech bad.
Not impressed. TSMC hit speed bumps with N3 and is slowing down. On the other hand now that Intel has turned their ship around they are going as fast as possible to surpass or match TSMC. Apple is dealing with the effects of TSMC hitting a wall, as their M silicon continues to grow in area gen after gen after gen as density gains are getting anemic.
@__aceofspades there no need to releae a new chip every year or 2 imo but they do it anyway wity minimal gains over the previous year's version
Why such a robot?? Are you an AI?
TSMC's announcements are coming fast and furious... meanwhile, at Intel... keep pushing those tech from years past will go into production... soon
dude, Intel is going to release 3 2nm products this year and another 3 next year.
they'll reach 18A and 14A before TSCM does 16A, the machines that make sub 2nm possible have all be bought by intel, which will make TSCM at least 6 months behind, if not more.
@@MaxIronsThirdIntel MTL & ARL CPUs use TSMC for 3 of the 4 Tiles. Intel’s Gaudi 3 AI GPU uses TSMC 5nm exclusively. Wake me up when Intel actually uses its own foundry.
Finally a commercial I'm excited about
haha true
Hey Dr Cuttess, if you want to improve your chroma keying, the key (heh) is to use more lights. The more/bigger the better. If you are filming with a camera that let's you film in raw or raw-like, or something like Sony's S-Log with high dynamic range, you can in post tone down the lighting so it looks natural. However, by having that much lighting, the camera picks up the color differences much better and the surfaces are lit in a more homogenous way, so the cutoff of your silhouette gets much sharper and not jittery.
In general, the more you can lower the ISO, the better, since a lower ISO means the camera does less guessing and colors are closer to real life. High ISO also introduces jitter and noise (bad for keying).
Good to know! It's already better than it used to be. One of my issues is that my office is only 12ft x 10ft - and most of that is storage for hardware. Leaves the area to film in very small
@@TechTechPotato yeah, that definitely complicates things. If there’s only one thing you can focus on, let it be having a uniform and strong lighting. Uniform as in lighting from various angles, so that there are no areas in shade confusing the camera/editor. Also prefer less but bigger lights to more but smaller lights, since for the same lumens, the bigger the source, the softer the shadows.
@@TechTechPotatomaybe get an office bigger than a toilet.
So TSMC is following Intel with the angstrom designation and Intel and TSMC both have pretty cool tech coming in the latter half of the decade... What's Samsung doing?
Sleeping.
more yummy silicon!
Educational videos on the various terms would be helpful
Yes!
System-on-wafer in production? Does it be Dojo for Tesla? They diagram looks even similar.
And I can't wait for progress of photonics, because IMHO it is what is next after silicon. Because with less power, it mean it can easily go 3D, and we don't talk about squares but cubics of compute.
Yup, Dojo was the first customer
they can do this without the new machine that Intel bought from ASML?
Intel bought the first 6 of them. No one else can get one until second half of next year.
no
I assume this A16 is going to be what Intel calls 18A.
I think (but I could be wrong) TSMC said something on the line "extreme UV is not required for sub 2nm nodes", so perhaps they don't need them, but it would be a bit strange that Intel spent so much money to book and buy the first 6 ASML machines if they were not essential. Or maybe TSMC is confident that this SPR can bring them to a node that matches intel's 18A, but without those machines
@@mastroitek Its true they do not need extreme UV for sub 2nm but in that case they can only make a chip half the size.
Moore’s law says the density of transistors doubles every two years because they get smaller. Therefore, less is Moore.
Hi, I’m not technical, but this one side for signalling and other side for power delivery, is it broadly similar to what Intel cals as backside power delivery that they are probably going to implement with PowerVia?
Tall and short standard cell libraries are pretty common at larger scales in my experience. Was it less common at these deep scales due to patterning requirements forcing very regular structures?
Is the SoW offering in any way related to Cerebras’ wafer scale engine technology?
It's more like Tesla's Dojo
@jonsnow111 I was wondering that too
Initially thought tsmc made an improved a16 bionic. Then came to know it was Angstrom. Been a long time, I heard angstrom unit in my physics lecture. 😂
Dr. Cultress, u need to grab one of those "Guai Guai" (乖乖) coconut-flavored edible chips from TSMC! That will be so funny eating them on air! Since TSMC engineers aren't allowed to eat nor film them inside the fab. :D
Dr. Ian is back with that big chip energy 😏
Oh no.. someone overclocked the outro music 😂
Well summarized what we can expect in the future with chip manufacturing overall besides what to expect from the industry leader TSMC. A16, more advanced MCM packaging and of course silicon photonics make all sense to be essential in the future.
The financing Intel (and others} is receiving from the federal government - is it non recourse - a grant - what might be the basic terms involved? Wondering }
Your chip is cute.
Imagine being in charge of an SOW 😬
wonder when we can expect the first video cards using A16 and how much extra cost we can expect on these chips production
this is a prime example of why you dont wear a thinly striped shirt when recording digital video.
But will it blend?
TSMC 도 Ayar labs 같은 방식을 도입하는군
TSMC just keeps on winning. I love it.
Shouldn't there be a big "SPONSORED" text somewhere in the title or in the video?
It's in the description, and on screen in the first few seconds. It's also part of the hashtags. Meets all UK OFCOM requirements, which are stricter than US FTC.
Props to you. I understand that getting text on top of the video is another step of work. I guess you could consider it anyhow. As you can always be excellent and not just passing the bar. Put your priorities where they matter to you and focus on being consistent whether you put disclaimers on screen. Inconsistency would be much worse as that will generate new conspiracies so i understand where you are coming from.
Good presentation,tsmc aiming 3D solution by stack up nano sheet aka cfet while Intel is trying High NA EUV to max the density in 2D way,will see who wins the battle
If you know so much then why you can't work in those companies?
A number of them have offered. But I like talking about everyone, not just one company.
TSMC on their back foot playing catchup with Intel. You have to give real credit to Pat Gelsinger with what he’s done since taking over.
Hahahahaha
3:50 uhhh... didnt intel say, several times, they can do this with their ribbonfet? Im pretty sure they did!
Tsmc didn't say they were the first to announce it
@@TechTechPotatoyou said no other company is talking about offering this in their design kits publicly... which is not true.
Oh sorry, I thought you were talking about bspdn with gaa. Yes I've read the Intel research on variable width ribbons, but they've not made an effort to codify it as an offering publicly.
@@TechTechPotato its in their marketting video where they show ribbonfet... (its on youtube. I think on their intel tech channel)
@@TechTechPotato ruclips.net/video/pymtOpvdRrI/видео.htmlfeature=shared