I am one of the software engineers that developed the software for it. I visited ASML EUV factory/cleanroom in Veldhoven a few months ago, there were EXE machines fully built and some other big modules being tested. It is amazing, you keep staring at it and each time you find something different about it. Making 10 nm features in high-volume is allien tech, it is almost half smaller than the current best high-volume process. In general, making features 50% smaller would reflect on 4x speed/performance or more logic, but because it is NA bigger only in one direction, the gain is limited to 2x. For Hyper-NA I think they are going for 4x gain.
the problem of slow progress is EXACTLY because corporations don't want to throw away these machines. it pays for itself in like a week of production of chips and they keep using them for DECADES milking the market instead of actually doing some FAST progress.
not making any progress and using these machines for decades = printing trillions $$$ from sand. just have to slow the progress down to being as slow as possible.
@@rawdez_the gains are a few orders of magnitude lower then that. Keep in mind, there are thousands of process steps to make a wafer useful and millions of dollars a year are spent on keeping these overcomplicated machines running. Go work for a fab and you’ll figure out it’s not all sunshine and roses.
When I applied for my graduation work (MSc, Eindhoven University of Technology), the assignment was to work on this machine. And this was still 1999... 25 years ago...
I was working as a Master student on a EUV prototype "lamp" at the RWTH Aachen, Fraunhofer ILT and a spin-off company those days. Interesting times full of advancements, miss it. I also miss the beautiful old Aachen city and region with all the culture, clubbing, "beer-gardens", great food, and nature for mountain-biking around. Never got such a good work/life balance in any other region I worked ever after. I should have stayed.
In 1999 at best you could get a DUV machine. this is an EUV machine. Twinscans were introduced around the year 2000 so you might have experienced that one...
check out Intel Tera herz - 1000GHz 2001 tech. these silicon producing machines should've been thrown into garbage a long time ago. for waaaay more mindblowing tech to replace it. but they make too much money for corporations so alas not going to happen soon.
@@rawdez_ I see a lot of comments from you and they are all a bit crazy. You write like things are very simple and you know everything. Intel is NOT making Billions on an investment of Millions. Intel is barely profitable. As for the terahertz transistor - that's ONE transistor, not a whole chip. A whole chip has billions of transistors... A terahertz CPU will, due to the speed of light, have information changing at one end of the chip while it's being processed at the other end. You can pipeline for this, somewhat, but pipelining is a very limited tool. Also, what about stability and longevity? The teraherts thing you know about is a fringe experiment... And you only hear about the one time it worked, not the hundreds of times it burnt the CPU, burnt the clock, etc...
@@-.369.- its 1000GHz transistors tech intel announced in 2001(apparently by mistake because nobody heard about it since 2001) that was ready for production and supposed to hit the market in 2005. and replace silicon. but didn't. because milking silicon instead is way more profits. btw "15nm" silicon tech also was announced as tested and working in 2001 but released (as 14nm) 13 years later.
Absolutely. It's literally holding the future in your hands. For ASML, their partners and their suppliers this is an incredible milestone, and this machine will pay Intel back for many years to come.
I would assume ASML also charges for handover and software to run the machine with or smth? Else why only sell it for 350 mil? Why is ASML worth 300+ billion whilst they only make maybe a dozen of these machines a year?
Def right cheap $350ml for such a complicated machine New tech has made things cheaper but creates a pile of throw away rubbish Make manufacturing back in your country
@@fatjohn1408 Company is usually quotting as having a worth related to its public/private stock market capitalization- which is very little to do with their actual assets on hand. Money generally only exchanges hands with investors to the company when stock is sold on the private market, or as IPO, or extra stock selloff
I was happy that RUclips recommended me this video. :) Like another commenter, I'm also a software engineer, but working farther away from the actual ASML machine, specifically developing a software platform for executing adjustment processes on the High NA EUV projection optics boxes. It's quite exciting to work on something that even just supports the manufacturing of these cutting edge machines. We had a tour at the Zeiss clean room, seeing both the older POBs and a new High NA EUV one, and this latter POB in itself is already gargantuan. It was an amazing experience. :)
Excellent purchase from Entel. This machine is incredible and Intel's progress forced TSM and Samdung to also place orders with ASML so as not to be left behind.
You missed some of the best bits, after vaporising the tin droplets you then need to stop the tin vapour from coating your $1M lenses...this was a very hard problem to solve!
Incredible how this technology is enabled by the top expertise from all over the world. The sector is so vast and so complex that it is unthinkable that one single country could manage all different aspects of high-tech semiconductor technology. Thank you Techtechpotato for producing this excellent video. Greetings from the UK, Anthony
Je me demande comment l'être humain est capable de fabriquer une machine qui dépasse son propre entendement. Comment organiser des dizaines de milliers de scientifiques, d'ingénieurs, de compétences pour parvenir à quelque chose d'aussi technologiquement avancé que cette machine.
Ngl I was thinking the same thing. Save up and build an experimental super low volume lab or something... Sadly, I'm sure even 1980s tech would be way out of any individual's price range.
In my previous job, I help spec a desktop for one of these machines at a smaller scale. The machine was 2.5million and I was told go crazy with the cores. That one definitely is extremely HUGE
If you get any invites to more Fabs, (don't care how new or old) go on ALL of those Fab tours. Just keep traveling and visiting. This is where the rubber meets the road, semiconductor fabrication.
It honestly both baffles me and restores my faith in humanity when I realize how much cooperation is needed to create and maintain something of this magnitude.
Wow you have an amazing curiosity on all of these stuffs at such a young age. I was video gaming at your age without carrying about any of these hardware stuffs.
Out of curiosity, how does the licensing work for those pictures taken by CBS? Like are they just released into the public domain or did each journalist/org on the tour get some kind of license? What kind?
@@BGraves Yes, I'm asking how sharing translates into licensing. I suspect they offered some kind of license to publish to those entities as well but is it unlimited, can they sublicense or did they just release it into the public domain?
love these kind of videos i think this device is human kind most advanced piece of tooling we build so far amazing to see it in perspective on how large it is, and as you mention this is not the full device i wonder if you could snap some images on the floor bellow.
Current metal pitch (from imec) in N5 is 28nm, using 6 metal tracks for FinFET. N2 is expected to be 21nm with 6 tracks, while A10 in 2028 is expected to be 16nm with 5 tracks. Though this is the densest IO transistors, not the leading edge super fast transistors.
This EUV chip manufacturing technology is probably the peak of cumalitive human technology? If there printing 10nm lines how come people are releasing 3nm and 5nm & 7nm in marketing theory, chip structures? is that in a different orthoganol direction … ie vertical to the wafer layer itself?
When you hear people talking about process nodes like 7nm, 5nm, 3nm, that's not an actual measurement, it's just a name. Ever since we went 3D, those node names aren't actually related to anything built on silicon.
It won’t be until 2026 at the earliest. Tenstorrent will remain private with the help of Samsung just like OpenAI will remain private with the help of Microsoft.
Not sure I follow your efficiency stuff @6:20 when you start with kWatts (power) and end with milliJoules/cm^2 (fluence). Units don't match and there is that 60 kHz pulse rate in there as well.
yes, the exact per pulse wafer dose is a commercially sensitive number. the input lasers aren't kWatt continuous, they are high repetition pulse - energy per pulse isn't said either.
I have some questions that I hope someone can answer for me. 1. Why does it require two passes with regular EUV? Is it because the light source is more diluted and can't do the job in one go? Or more like its a bit blurry? 2. From my memory of chemistry at university, 8nm should equate to about 40 pr 50 atoms. How on earth do you prevent or control all kinds of weirdness that result from electron tunneling? 3. Are we basically at the fundamental limit of how small we can go? If so is it just how well the architecture can be improved, and how much can AI improve it, or will it become a case of stacking layers on top of layers, potentially with microstructures that allow more efficient cooling?
For your number one, it might be because of multi-pattering. In short, you can create structure smaller than your wavelength if you multi-pattern onto the silicon. Basically you're multi-exposing your photo resist to create structures you can't make with a single reticle/mask at that wavelength. It's rumored that pattering is how china is somehow managing to keep up with EUV despite not having current euv tools. That might not be what Ian was talking about though.
@@Alex.The.Lionnnnn The best that I can put it is this: Using phase shift masks we are taking advantage of interference in order to etch features that are much smaller than the wavelength allowing for example the etching trench line that is just 8 nanometers wide (your line width) in the silicon. Remember in a positive photoresist such as used in EUV, its the exposed parts that get etched away. The problem is due to the Raleigh criterion you cannot etch your 8 nm wide line closer than 50 nm (your pitch) from each other if you have low-NA (0.33) EUV. Now if you etch your first set of lines, coat it again with photoresist expose another pattern this time offset just enough so that it etches right in the middle between the lines that you previously etched. You now have pitch of 25 nm. You can now pack twice the number of lines in the same space. Repeat the process you now have a pitch of 12.5 nm. In practical terms where you where previously limited to a finFET with a 50 nm wide fins, by using 3 patterns you now have 12.5 nm fins. If you have a higher NA you can have a finer pitch with having to resort to as many patterns and exposures.
Numbers are bit inaccurate on the laser itself - there is 4 Resonators that step up the 2 smaller lasers ( baby lasers!) bringing a low power then an additional smaller amplifier to around ~150 watts all the way to an Average output power of ~30kW. The Pulse for the flattening is lower powered - but the Pulse that creates the EUV can be around 20MW per pulse! (think, we are averaging across 50 khz) but still - incredibly powerful - one of the resonators can cut through 2 inches of steel with ease - and CYMER/ASML/TRUMPF said... lets put 4 of them together! Look up TRUMPF EUV for a better understanding of the laser itself!
i used to work in f11, f12 and f22. i worked with D2 people in oregon. crazy that they're a month behinds asml. very smart of them to get their engineer's feet wet as clearly they got out of shape re: euv in general. decisions like that tended to bear fruit. we would literally do the same thing downstream for the high vol mfg sites training from the d2 folks as they did development.
A good size comparison would be to a train locomotive. Basically, those things are trains, just they make microchips instead of hauling goods and people.
It's really exciting to see Intel not only being the first to adopt High-NA EUV, but to have ordered the majority of machines ASML is making. Pat Gelsinger really seems like the right person to lead Intel into the future, as he understands that a leading edge fab needs to lead, as then their own chips end up great and competition will want to pay them for fab capacity, so Intel wins all around.
not having to pay to other manufacturers for production of your chips $20k/wafer skyrockets your profit margins. when nv has to pay $200 for a 4090 chip (yes, its exactly how much it costs to make a 4090 $2000 GPU chip, probably even less now) to TSMC or Samsung, Intel just rakes in all the profits. and with 185 wafers/h @$20k/wafer price $350 mil machine pays for itself in 4 days. literally.
It is a huge bet. However I don't see Intel succeeding as a fab service provider. It is not like they didn't try that before. The PC market is less then booming. On top of that the x86 architecture is being now seriously at the brink of being phased out. What do they have that they want to fill those production lines with? And in esp. what can they offer that actually requires the latest node to be competitive in production?
@@rosomak8244 you can produce any chips with these machines. its not locked somehow to only x86 chips production. the main Intel fab client is Intel and they are safe. PC market is less then booming due to GPUs having 0 progress and being overpriced because corporations raised prices for miners and 'forgot' (didn't want to) to drop them back after mining was gone. basically nv sells 4 times less GPUs but for 4 times money more each so they are fine. just like everyone else. they sell way less then before but make way more profits than ever. Intel actually didn't try that before because they've chose to milk 14nm ++++++ instead as way more profitable approach of making business at the time. but eventually got kicked a bit by Ryzen, so they were forced to change because the market has changed. also they got into GPU business just because they've seen insane nv/amd margins. and they know those margins are insane because they run fabs themselves and know exactly how (really not that) much it cost to make those chips.
@@rosomak8244 you can produce any chips with these machines. its not locked somehow to only x86 chips production. the main Intel fab client is Intel and they are safe.
@@rosomak8244 PC market is less then booming due to GPUs having 0 progress and being overpriced because corporations raised prices for miners and 'forgot' (didn't want to) to drop them back after mining was gone. basically nv sells 4 times less GPUs but for 4 times money more each so they are fine. just like everyone else. they sell way less then before but make way more profits than ever.
@10:55 Although you probably singed an NDA, you know what other machines you saw inside the fab. I would guess even some Japanese equipment manufactures.
I think it's safe to say that the next High-NA machine isn't going to China, unless you're Elon Musk and consider Taiwan as part of China. I think I had already read that ASML is going to work closely with Intel to ensure this gets up and running properly so we can assume there's other money involved. And Intel REALLY needs this because they mucked up EUV. And for those that don't understand this, Intel is making "Intel 7" with DUV lithography. They're making Intel 4 with EUV, but as of yet Intel 4 isn't making anything for desktop. I don't know the answer why. They had a LOT of issues getting to Intel 7 using DUV but that should have been expected since that "7" node is not what DUV lithography was made for. EUV lithography was made for that type of transistor density which is what TSMC does and why TSMC has pulled away from other companies. So, I expect that Intel wants to basically jump past EUV and get to High-NA EUV and put out Intel 3 and 20A ASAP to get back on the level of TSMC. Or, if this video is correct then have ASML help Intel with their EUV lithography so they can put out Intel 3 within the next couple years and I still think they want to get to High-NA for 20A regardless of what they say or their roadmap shows. Intel has had to do a LOT of edits to their roadmaps.
I wonder if Intel was also stuck on EUV, because TSMC had developed a technique of working with it and patented it and Intel didn't want to be stuck with using someone else's patented technology for this...?
I didn't even watch this but whoever the guy in the thumbnail is, he gets an instant penalty for not having his nose tucked into his cleanroom suit. How did this blatant demonstration of employee failure end up featured on the poster??
@@TechTechPotato He's probably never suited up and is about five pay grades above the guy who should have slapped him for not following gowning protocol 😄
TBH I have never doubted the competence of Intel brilliant engineers. I just hope the incompetent management didn't mismanage for too long and it's too late to make the fab business to turn around even though how amazing the engineering team are. We wouldn't want either TSMC or Intel become monopoly player after all.
you don't immediately use new wavelengths to create your latest chips. New nodes are only used in specific layers, and there can be dozens of layers in a single chip. So today's cutting edge chips are only using EUV for maybe 2-3 layers. The rest are "old" nodes.
Question - what about vibration isolation? Was this machine built on its own support? Was hydraulic suspension or dampers used? Did they have to re route aby truck traffic? Are the machine getting more vibration insensitive or vibration sensitive ??
Worked in this industry for over a decade. Safe to say that vibration is a big no no.. So almost all these machines sit on their own isolation platforms with actively controlled levelling and stabilisation systems.
@@AmrishKelkar Thanks. Just the leveling and vibration isolation could be an interesting video. with smaller features, it seems external truck and internal parts moving Vibrations becomes a larger issue.
the entire fab is seismically isolated, as is every floor in the fab, as are the tools themselves. To tell you how sensitive the tools in the fab are to vibration, we often know in the fab about earthquakes before we hear it on the news. Quakes in Alaska and Japan will cause some lithography tools to error out. So yeah, the buildings are incredibly vibration protected and it still often isn't enough.
That's marketing, most new tech is 10nm but since they are making 3D fets (think of turning the parts on side-edge...they call it next generation for lay people.
Correction on the title , Intel buy $350 million chip making machine from ASML. Now i seems like they made it. ASML HQ isn't even in the states although admitted it does contain american patented parts and Intel does own ASML stock like TSMC and samsung.
I have read that Intel's newest machine is the prototype of what they are going to get. To test out this tech. So the production machine is still coming.
The complexity of this thing is obvious from looking at it. There are many parts put together hat do not repeat in a regular pattern. Nothing is there that shouldn't be for a definite purpose.
![[32] Ian Interviews: Pat Gelsinger, Intel CEO](/img/1.gif)
I am one of the software engineers that developed the software for it. I visited ASML EUV factory/cleanroom in Veldhoven a few months ago, there were EXE machines fully built and some other big modules being tested. It is amazing, you keep staring at it and each time you find something different about it. Making 10 nm features in high-volume is allien tech, it is almost half smaller than the current best high-volume process. In general, making features 50% smaller would reflect on 4x speed/performance or more logic, but because it is NA bigger only in one direction, the gain is limited to 2x. For Hyper-NA I think they are going for 4x gain.
185 wafers/h @$20k = $3,7 mil/h. it will return its $350 Mill cost in 4 days.
intel tera herz in Intel vault of future tech is collecting dust from 2001. while corporations are milking funny low sillicon gains for decades.
the problem of slow progress is EXACTLY because corporations don't want to throw away these machines. it pays for itself in like a week of production of chips and they keep using them for DECADES milking the market instead of actually doing some FAST progress.
not making any progress and using these machines for decades = printing trillions $$$ from sand. just have to slow the progress down to being as slow as possible.
@@rawdez_the gains are a few orders of magnitude lower then that. Keep in mind, there are thousands of process steps to make a wafer useful and millions of dollars a year are spent on keeping these overcomplicated machines running. Go work for a fab and you’ll figure out it’s not all sunshine and roses.
Many of my university friends work at Zeiss now building these EUV optics :)
And we put them to use 😋
The most precise optics ever created, way beyond the hubble lens.....damn right you're not humble about it 😄
It's mirrors, not lenses :) no more lenses possible at 13,5nm.. @paulmichaelfreedman8334
When I applied for my graduation work (MSc, Eindhoven University of Technology), the assignment was to work on this machine. And this was still 1999... 25 years ago...
lol, and Intel tera herz 1000GHz leak was in 2001, 23 years ago.
I was working as a Master student on a EUV prototype "lamp" at the RWTH Aachen, Fraunhofer ILT and a spin-off company those days. Interesting times full of advancements, miss it. I also miss the beautiful old Aachen city and region with all the culture, clubbing, "beer-gardens", great food, and nature for mountain-biking around. Never got such a good work/life balance in any other region I worked ever after. I should have stayed.
It feels like Intel has been on 10nm for that long as well💀
i think you are colleague of my father, he works on ASML since ASM collaborate with phillips
In 1999 at best you could get a DUV machine. this is an EUV machine. Twinscans were introduced around the year 2000 so you might have experienced that one...
The things humans can make is kind of wild
check out Intel Tera herz - 1000GHz 2001 tech. these silicon producing machines should've been thrown into garbage a long time ago. for waaaay more mindblowing tech to replace it. but they make too much money for corporations so alas not going to happen soon.
Intel tera herz example shows that its even more wild what humans can make but just don't for some stupid reasons. like a lot of trillions dollars))
@@rawdez_ I see a lot of comments from you and they are all a bit crazy. You write like things are very simple and you know everything. Intel is NOT making Billions on an investment of Millions. Intel is barely profitable.
As for the terahertz transistor - that's ONE transistor, not a whole chip. A whole chip has billions of transistors... A terahertz CPU will, due to the speed of light, have information changing at one end of the chip while it's being processed at the other end. You can pipeline for this, somewhat, but pipelining is a very limited tool.
Also, what about stability and longevity?
The teraherts thing you know about is a fringe experiment... And you only hear about the one time it worked, not the hundreds of times it burnt the CPU, burnt the clock, etc...
@@rawdez_ whats a Intel Tera herz - 1000GHz tech?
@@-.369.- its 1000GHz transistors tech intel announced in 2001(apparently by mistake because nobody heard about it since 2001) that was ready for production and supposed to hit the market in 2005. and replace silicon. but didn't. because milking silicon instead is way more profits. btw "15nm" silicon tech also was announced as tested and working in 2001 but released (as 14nm) 13 years later.
You must have felt like a kid in the best candy store in the history of this planet.
He does have a taste for chips if the photos are anything to go by
Im just surpised its already installed. Intel got the machine in mid January and they are already this far. Serious business ^^
What is the point of gowning up if you leave your nose exposed and spraying nascal droplets everywhere?
350mil is bloody cheap for a industrial machine this sophisticated.
Absolutely. It's literally holding the future in your hands. For ASML, their partners and their suppliers this is an incredible milestone, and this machine will pay Intel back for many years to come.
I would assume ASML also charges for handover and software to run the machine with or smth?
Else why only sell it for 350 mil?
Why is ASML worth 300+ billion whilst they only make maybe a dozen of these machines a year?
M or mi*
Def right cheap $350ml for such a complicated machine
New tech has made things cheaper but creates a pile of throw away rubbish
Make manufacturing back in your country
@@fatjohn1408 Company is usually quotting as having a worth related to its public/private stock market capitalization- which is very little to do with their actual assets on hand. Money generally only exchanges hands with investors to the company when stock is sold on the private market, or as IPO, or extra stock selloff
I was happy that RUclips recommended me this video. :) Like another commenter, I'm also a software engineer, but working farther away from the actual ASML machine, specifically developing a software platform for executing adjustment processes on the High NA EUV projection optics boxes. It's quite exciting to work on something that even just supports the manufacturing of these cutting edge machines. We had a tour at the Zeiss clean room, seeing both the older POBs and a new High NA EUV one, and this latter POB in itself is already gargantuan. It was an amazing experience. :)
Oh that's nice! I'd love a tour of Zeiss. (that rhymes!)
I'll see if my new ASML contact can get me in.
Ian is the champion of breaking down complex topics so even dorks like me can understand them.
ASML have shipped Twinscan EXE:5000, this is great news.
Thanks for keeping us in the (k)now
Excellent purchase from Entel. This machine is incredible and Intel's progress forced TSM and Samdung to also place orders with ASML so as not to be left behind.
The math, chemistry, physics, engineering and technology in these things is off the chart crazy.
You missed some of the best bits, after vaporising the tin droplets you then need to stop the tin vapour from coating your $1M lenses...this was a very hard problem to solve!
I've heard stories, perhaps a topic for a future video!
@@TechTechPotatoWe probably will never know the names of the genius who figured it out.
@@mefobills279Probably a team effort
Been there, done that 15 years ago.
Incredible how this technology is enabled by the top expertise from all over the world. The sector is so vast and so complex that it is unthinkable that one single country could manage all different aspects of high-tech semiconductor technology.
Thank you Techtechpotato for producing this excellent video.
Greetings from the UK,
Anthony
Je me demande comment l'être humain est capable de fabriquer une machine qui dépasse son propre entendement.
Comment organiser des dizaines de milliers de scientifiques, d'ingénieurs, de compétences pour parvenir à quelque chose d'aussi technologiquement avancé que cette machine.
11:10 I wish I could buy a 250nm machine from 1980s for home use.
Ngl I was thinking the same thing. Save up and build an experimental super low volume lab or something... Sadly, I'm sure even 1980s tech would be way out of any individual's price range.
Check out the work by Sam Zeloof. He built 1000 transistor chips in his Garage at the age of 18.
You will need about 15k in eBay parts but is possible
I bet with stamps using nano-imprint methods you could make a few tiny transistors. Connecting them together might be more difficult. 😮
I think the chemicals even 250nm machines use for their UV lasers would be difficult to manage.
In my previous job, I help spec a desktop for one of these machines at a smaller scale. The machine was 2.5million and I was told go crazy with the cores. That one definitely is extremely HUGE
The inventor of lithography was Alois Senefelder 1794-1798. His invention is continuously perfected by ASLM and there is no end in sight.
If you get any invites to more Fabs, (don't care how new or old) go on ALL of those Fab tours. Just keep traveling and visiting. This is where the rubber meets the road, semiconductor fabrication.
Now working for ASML. The equipment is very precise. Just the LASER for it is huge and has some serious IP in it's R&D.
It honestly both baffles me and restores my faith in humanity when I realize how much cooperation is needed to create and maintain something of this magnitude.
The Sub-fabs are just like stacked chips which is pretty cool lol, great video Ian.
What did it taste like? They let you take a bite right?
Thanks for pronouncing Oregon correctly!
I’m just a typical application development software engineer, I don’t have anything to do with this stuff, but i love learning about it
that's so cool to catch a glimpse into a fab and actually see the latest asml euv fab machine.
I'd love if you could bring us a tour of an OLED fab.
me too!
Gamers Nexus did some cool tours
Wow you have an amazing curiosity on all of these stuffs at such a young age. I was video gaming at your age without carrying about any of these hardware stuffs.
Dude I'm almost 40.
@@TechTechPotato in his context almost 40 is young. He's probably 70 or 80 now. /s
Amazing. Best of luck to their facilities.
Flown to Seattle? I'd love to know why they couldn't fly it into PDX and just drive it the 10 miles to the fab from the airport. Seems kinda weird.
Or just fly into Hillsboro across the street from the fab
I have landed many times at Hillsboro. No 747 can land there. We move the scanner in a 747
@@arrdubuHillsboro runway is 6600ft. SEATAC is 8500-11900ft. A fully loaded 747 requires about 10000ft of runway. Not possible.
PDX might not have the support infrastructure to unload. SEA is a much larger airport with more capabilities.
@@CyrusTabery I've watched many 747s and other large aircraft land at Hillsboro.
That's all very well, but does it make good gravy?
so at what point does it stop being ultraviolet and start being xrays?
EUV was actually called 'soft xray' back in the 80s. The designation is largely arbitrary.
According to a NASA xray science page i found, xrays are 0.03 - 3nm.
lol I am the guy that yelled at you guys for one of your hoods being inside out! 😂
hell yeah, this was cool as heck and super informative, thank you for this quality content.
What happens to the vaporised tin droplets? I would assume they would cause a build-up of matter on surrounding surfaces.
I believe they do, to a certain extent.
Out of curiosity, how does the licensing work for those pictures taken by CBS? Like are they just released into the public domain or did each journalist/org on the tour get some kind of license? What kind?
He said that everyone in the tour is required to share their media with everyone else including Intel
@@BGraves Yes, I'm asking how sharing translates into licensing. I suspect they offered some kind of license to publish to those entities as well but is it unlimited, can they sublicense or did they just release it into the public domain?
love these kind of videos i think this device is human kind most advanced piece of tooling we build so far amazing to see it in perspective on how large it is, and as you mention this is not the full device i wonder if you could snap some images on the floor bellow.
You are really great. while you describe your visits to foundries, it feels like being there...
This video just blew my mind, earned my sub
What is the connection between ASML 8nm lines and the process for CPUs declared by Intel/tsm?
Current metal pitch (from imec) in N5 is 28nm, using 6 metal tracks for FinFET. N2 is expected to be 21nm with 6 tracks, while A10 in 2028 is expected to be 16nm with 5 tracks. Though this is the densest IO transistors, not the leading edge super fast transistors.
@@TechTechPotatoIt’s amazing that ASML can achieve 16nm metal pitch in A10. How will the A10 process mitigate electromigration?
@@tringuyen7519 agreed I think this would be an issue, how do they fix?
Think i read : Intel just adds a text these chips will fail after 50.000 hours i think. That like 3.4ish years of run time.
This EUV chip manufacturing technology is probably the peak of cumalitive human technology? If there printing 10nm lines how come people are releasing 3nm and 5nm & 7nm in marketing theory, chip structures? is that in a different orthoganol direction … ie vertical to the wafer layer itself?
When you hear people talking about process nodes like 7nm, 5nm, 3nm, that's not an actual measurement, it's just a name. Ever since we went 3D, those node names aren't actually related to anything built on silicon.
@@TechTechPotato - you should have mentioned that in the video.
I thought straight away - what about 3nm chips?
I did? I mentioned node names are just names, not actual dimensions. I've said it in dozens of videos.
@@TechTechPotato - OK - I missed that.
You are speaking to lay people not semiconductor experts.
I know this is off topic, but any indication that Tenstorrent is going to go public?
It won’t be until 2026 at the earliest. Tenstorrent will remain private with the help of Samsung just like OpenAI will remain private with the help of Microsoft.
Thank You For Your Presentation!
im laughing, i thought it was the trailer for dune 3, nice video, thank you!
Not sure I follow your efficiency stuff @6:20 when you start with kWatts (power) and end with milliJoules/cm^2 (fluence). Units don't match and there is that 60 kHz pulse rate in there as well.
yes, the exact per pulse wafer dose is a commercially sensitive number. the input lasers aren't kWatt continuous, they are high repetition pulse - energy per pulse isn't said either.
I have some questions that I hope someone can answer for me.
1. Why does it require two passes with regular EUV? Is it because the light source is more diluted and can't do the job in one go? Or more like its a bit blurry?
2. From my memory of chemistry at university, 8nm should equate to about 40 pr 50 atoms. How on earth do you prevent or control all kinds of weirdness that result from electron tunneling?
3. Are we basically at the fundamental limit of how small we can go? If so is it just how well the architecture can be improved, and how much can AI improve it, or will it become a case of stacking layers on top of layers, potentially with microstructures that allow more efficient cooling?
For your number one, it might be because of multi-pattering. In short, you can create structure smaller than your wavelength if you multi-pattern onto the silicon. Basically you're multi-exposing your photo resist to create structures you can't make with a single reticle/mask at that wavelength.
It's rumored that pattering is how china is somehow managing to keep up with EUV despite not having current euv tools.
That might not be what Ian was talking about though.
@@CRneu but how? It doesn't make sense.
@@Alex.The.Lionnnnn The best that I can put it is this: Using phase shift masks we are taking advantage of interference in order to etch features that are much smaller than the wavelength allowing for example the etching trench line that is just 8 nanometers wide (your line width) in the silicon. Remember in a positive photoresist such as used in EUV, its the exposed parts that get etched away. The problem is due to the Raleigh criterion you cannot etch your 8 nm wide line closer than 50 nm (your pitch) from each other if you have low-NA (0.33) EUV. Now if you etch your first set of lines, coat it again with photoresist expose another pattern this time offset just enough so that it etches right in the middle between the lines that you previously etched. You now have pitch of 25 nm. You can now pack twice the number of lines in the same space. Repeat the process you now have a pitch of 12.5 nm. In practical terms where you where previously limited to a finFET with a 50 nm wide fins, by using 3 patterns you now have 12.5 nm fins. If you have a higher NA you can have a finer pitch with having to resort to as many patterns and exposures.
@noob360 ahhhh ok I'm with you. Cheers.
Numbers are bit inaccurate on the laser itself - there is 4 Resonators that step up the 2 smaller lasers ( baby lasers!) bringing a low power then an additional smaller amplifier to around ~150 watts all the way to an Average output power of ~30kW. The Pulse for the flattening is lower powered - but the Pulse that creates the EUV can be around 20MW per pulse! (think, we are averaging across 50 khz) but still - incredibly powerful - one of the resonators can cut through 2 inches of steel with ease - and CYMER/ASML/TRUMPF said... lets put 4 of them together! Look up TRUMPF EUV for a better understanding of the laser itself!
Imagine the truck driver looking at his cargo sheet and seeing the cargo value when transporting these machines 😳
Impressive archivement both ASML and Intel for trying to push the boarders of modern lithography even further.
Its a miracle that something doesn't break at least once a day on that machine!
Always enjoy the fab visits and I'm really hoping you'll get a chance to hit up Intel's packaging facility in New Mexico.
Worked on semiconductor equipment in fabs for 20 year. Loved it
i used to work in f11, f12 and f22. i worked with D2 people in oregon. crazy that they're a month behinds asml. very smart of them to get their engineer's feet wet as clearly they got out of shape re: euv in general. decisions like that tended to bear fruit. we would literally do the same thing downstream for the high vol mfg sites training from the d2 folks as they did development.
And they made, shipped, installed and run everything with solar panels. It's amazing they can do all this with net zero.
It really is mind blowing just how small these parameters are.
If you shed an eyelash, you're spoiling an awful lot of stuff.
I wonder what's the current line width in R&D? A nice plot would be cpk vs line width. or a results from a field exposure matrix.
I love how in all these ASML videos there’s always someone who says they worked on something.
we're everywhere!!
True, trey either are very proud of being involved or they are lying and wish they were actually involved.
A good size comparison would be to a train locomotive. Basically, those things are trains, just they make microchips instead of hauling goods and people.
It's really exciting to see Intel not only being the first to adopt High-NA EUV, but to have ordered the majority of machines ASML is making. Pat Gelsinger really seems like the right person to lead Intel into the future, as he understands that a leading edge fab needs to lead, as then their own chips end up great and competition will want to pay them for fab capacity, so Intel wins all around.
not having to pay to other manufacturers for production of your chips $20k/wafer skyrockets your profit margins. when nv has to pay $200 for a 4090 chip (yes, its exactly how much it costs to make a 4090 $2000 GPU chip, probably even less now) to TSMC or Samsung, Intel just rakes in all the profits. and with 185 wafers/h @$20k/wafer price $350 mil machine pays for itself in 4 days. literally.
It is a huge bet. However I don't see Intel succeeding as a fab service provider. It is not like they didn't try that before. The PC market is less then booming. On top of that the x86 architecture is being now seriously at the brink of being phased out. What do they have that they want to fill those production lines with? And in esp. what can they offer that actually requires the latest node to be competitive in production?
@@rosomak8244 you can produce any chips with these machines. its not locked somehow to only x86 chips production. the main Intel fab client is Intel and they are safe.
PC market is less then booming due to GPUs having 0 progress and being overpriced because corporations raised prices for miners and 'forgot' (didn't want to) to drop them back after mining was gone. basically nv sells 4 times less GPUs but for 4 times money more each so they are fine. just like everyone else. they sell way less then before but make way more profits than ever.
Intel actually didn't try that before because they've chose to milk 14nm ++++++ instead as way more profitable approach of making business at the time. but eventually got kicked a bit by Ryzen, so they were forced to change because the market has changed.
also they got into GPU business just because they've seen insane nv/amd margins. and they know those margins are insane because they run fabs themselves and know exactly how (really not that) much it cost to make those chips.
@@rosomak8244 you can produce any chips with these machines. its not locked somehow to only x86 chips production. the main Intel fab client is Intel and they are safe.
@@rosomak8244 PC market is less then booming due to GPUs having 0 progress and being overpriced because corporations raised prices for miners and 'forgot' (didn't want to) to drop them back after mining was gone. basically nv sells 4 times less GPUs but for 4 times money more each so they are fine. just like everyone else. they sell way less then before but make way more profits than ever.
And Thanks to VDL ETG Eindhoven, for making the Vessel and OPframe. 😎
It will more than pay for itself
in 4 days. with 185 wafers/h @$20k/wafer price $350 mil machine pays for itself in 4 days. literally.
How is 0.33nm smaller than 0.55nm? Was it a mistake in the vid?
0.33 or 0.55 isn't a nm. It's the numerical aperture. A dimensionless unit that goes into the wavelength equation.
Great video for the most advanced chip maker technology, also like to see the comments from all of you folks 👍🏻👍🏻
@10:55 Although you probably singed an NDA, you know what other machines you saw inside the fab. I would guess even some Japanese equipment manufactures.
Amat sold certain things to Korea, so Korea is now a major manufacturer of equipment.
I think it's safe to say that the next High-NA machine isn't going to China, unless you're Elon Musk and consider Taiwan as part of China.
I think I had already read that ASML is going to work closely with Intel to ensure this gets up and running properly so we can assume there's other money involved.
And Intel REALLY needs this because they mucked up EUV. And for those that don't understand this, Intel is making "Intel 7" with DUV lithography. They're making Intel 4 with EUV, but as of yet Intel 4 isn't making anything for desktop. I don't know the answer why. They had a LOT of issues getting to Intel 7 using DUV but that should have been expected since that "7" node is not what DUV lithography was made for. EUV lithography was made for that type of transistor density which is what TSMC does and why TSMC has pulled away from other companies.
So, I expect that Intel wants to basically jump past EUV and get to High-NA EUV and put out Intel 3 and 20A ASAP to get back on the level of TSMC. Or, if this video is correct then have ASML help Intel with their EUV lithography so they can put out Intel 3 within the next couple years and I still think they want to get to High-NA for 20A regardless of what they say or their roadmap shows. Intel has had to do a LOT of edits to their roadmaps.
I wonder if Intel was also stuck on EUV, because TSMC had developed a technique of working with it and patented it and Intel didn't want to be stuck with using someone else's patented technology for this...?
Taiwan is part of China. That was settled when Nixon went there to triangulate against the Soviets. Engineers are supposed to be data driven.
Amazing! I couldn't understand a single word in this video but amazing ❤
isn't 13nm last century? is that the metal pitch number, it's confusing because reading more 2nm is marketing.
Mostly ancient Minoan to me, but if it results in powerful graphics that can run on AAA batteries then money well spent.
I didn't even watch this but whoever the guy in the thumbnail is, he gets an instant penalty for not having his nose tucked into his cleanroom suit. How did this blatant demonstration of employee failure end up featured on the poster??
If you'd watched, you'll realise it's me. Then notice how the head of lithography if Intel, shown 2/3 of the way through, also does the same thing
@@TechTechPotato He's probably never suited up and is about five pay grades above the guy who should have slapped him for not following gowning protocol 😄
😂😂
The fact that the first thing that came to mind from that blurred background was High NA says something ig
TBH I have never doubted the competence of Intel brilliant engineers. I just hope the incompetent management didn't mismanage for too long and it's too late to make the fab business to turn around even though how amazing the engineering team are.
We wouldn't want either TSMC or Intel become monopoly player after all.
If you fractor in the sells of chips, this is ACTUALLY one of the most advanced and expensive piece of equipment
TSMC and probably SMIC will likely do it again if this final wunderwaffe of lithography doesn't, for the love of god; give back leading edge to Intel.
I wouldn't be surprised if the vast majority of exposures on modern CPUs are still done with DUV
They still are. A modern 17 layer chip uses EUV for only the first 2-4 or perhaps 6.
you don't immediately use new wavelengths to create your latest chips. New nodes are only used in specific layers, and there can be dozens of layers in a single chip. So today's cutting edge chips are only using EUV for maybe 2-3 layers. The rest are "old" nodes.
I worked in that building, in the basement. That's where the pumps are located.
you gave a informative discription of wafer fabbing
I do not understand how people can make so many fascinating things.
3:08 “Standard normal sized people” had me 💀
Question - what about vibration isolation? Was this machine built on its own support? Was hydraulic suspension or dampers used? Did they have to re route aby truck traffic?
Are the machine getting more vibration insensitive or vibration sensitive ??
Worked in this industry for over a decade. Safe to say that vibration is a big no no.. So almost all these machines sit on their own isolation platforms with actively controlled levelling and stabilisation systems.
@@AmrishKelkar Thanks.
Just the leveling and vibration isolation could be an interesting video. with smaller features, it seems external truck and internal parts moving Vibrations becomes a larger issue.
the entire fab is seismically isolated, as is every floor in the fab, as are the tools themselves. To tell you how sensitive the tools in the fab are to vibration, we often know in the fab about earthquakes before we hear it on the news. Quakes in Alaska and Japan will cause some lithography tools to error out.
So yeah, the buildings are incredibly vibration protected and it still often isn't enough.
@@CRneu "Quakes in Alaska and Japan " cause errors. Wow.
Nothing like a real world report
Great video 👍🏻👏🏻👏🏻👏🏻
Very well done. Most impressive :)
3:28 You bred raptors?
You are saying 10nm but isn’t TSMC already making 3nm chips and smaller?
That's marketing, most new tech is 10nm but since they are making 3D fets (think of turning the parts on side-edge...they call it next generation for lay people.
that thumbnail caption, hahaha :D
Correction on the title , Intel buy $350 million chip making machine from ASML. Now i seems like they made it. ASML HQ isn't even in the states although admitted it does contain american patented parts and Intel does own ASML stock like TSMC and samsung.
can we assume that Arrow Lake is using this new machine ?
Wonder what game graphics would look like this machine
Can’t imagine the PMs on this thing
What was the old $350 Million machine?
love it when a tech has a chair ,
Must be our Dutch pride ASML
The money numbers are definitely headed in the direction of pentagon sized money numbers
How long before this will be ready for an operating production line. Would 2 years be a correct estimate?
Well I mention that in the video, even put up a slide
@@TechTechPotato I know, I posted before watching the full video
How long will it be?
Awww.... I could have given you the tour!
Next time!
I have read that Intel's newest machine is the prototype of what they are going to get. To test out this tech. So the production machine is still coming.
Its amazing to me that a machine that big is needed to make a small chip
Would be amusing if the tin droplet feed worked like a shot tower.
is this the EXE:5000 or the EXE:5200? should be the 5000 right?
5000 indeed.
Would be interesting to see if the machine comes with an IKEA style assembly booklet.
Funnily enough, I did ask if it did
DEI had no part in the creation of this machine, only the merits of brilliant individuals
The complexity of this thing is obvious from looking at it. There are many parts put together hat do not repeat in a regular pattern. Nothing is there that shouldn't be for a definite purpose.
Some 25ish years ago I got to tour a DuPont fab