It brings back some almost forgotten memories. Around 1991 I worked for 6 years in the Waferfab Automation Department of Philips Semi Conductors Industry in Nijmegen, now Nexperia-ITEC. In that time we had a lot of contacts with the Philips Research Lab and AMSL a former part of Philips both in Eindhoven. A colleague went for 1 year to TMSC Taiwan. I lived in interesting times!
My main question here being - Even if you can control semiconductor like if it can conduct or not [9:40], it's done when current is passed through it or not. But a conductor by definition is something which conducts WHEN current is passed through it.. so isn't semiconductor just a conductor at all times except when it's not doing anything in which case, it shouldn't even matter if it's conductor or not
Thank you so much for making these videos. I find the whole idea of mobile phones and laptops so fascinating due to how much they’re able to do, but I’ve never understood how they were able to work. With Apple releasing the M1 chip I’ve become more interested in learning about it and your videos are really good at explaining the basics. I still find myself getting a bit lost with some of the more technical terms but I usually look them up if I’m not feeling too lazy haha.
19:13 Semiconductor chips are one of the most precisely engineered things we see in daily life. Imagine how well-engineered and precise the machines that make the chips need to be.
I had no idea of the complexities involved in the manufacture of a cpu. It certainly makes you realize the things we take for granted! An amazing video! Thank you Gary!
Very, very interesting informations and explanations. I really din't know the difference of numbers of transistors in a lithography type, amongst the manufacturing companies. I thought it was a standard thing! Thanks for all the efford and research!
I know there wasn't time to go into much detail about transistors, but in 9:08 the symbol on the left is for a bipolar junction transistor (BJT), while the illustration on the right is of a field effect transistor (FET). These are different designs. In particular, the FET is a voltage-driven device. There's a *voltage* applied to the middle pin, but it doesn't result in any *current* flowing to or from the middle pin. A really cool elaboration on this design is to leave a disconnected gate in a FET, and then you get flash memory.
A great video Gary - Excellent summary about making modern CPUs - very compact but never the less extremely extensive content. I was kind of shocked that all big CPU manufactures TSMC, Samsung and even Intel are dependent on just one company worldwide that is able to produce these extreme ultra violet lithography machines. It's the ASML Holding (en.wikipedia.org/wiki/ASML_Holding) in the Netherlands NOT Denmark. In other words, the hole 'silicon' world depends on just one single point of failure. This is quite scary to me.
The world is a complicated place. Apple and Samsung are obviously competitors, so I was blown away when I learned that Samsung made the screen for the iPhone X. As we have learned in the last year, global supply chains are highly integrated and optimized for regular flow, meaning any disturbances propagate all over.
Wow! Been looking for this info for so long. Thank you! Now to find how cpu cache and instructions work and how it’s implemented in these tiny transistors
Thanks Gary, that’s beyond academic grade education. Your way of articulating the info for your topics could land to a degree. I don’t know how up to date Intel’s finfet is, but a comparison to their processes with the ASML machine would be awesome to learn.
FinFet has been the standard for all chips, however to make chips smaller this will need to be replaced with GAA = Gate All around. This however has more to do with chip design, not so much with the ASML machine.
This is very interesting and I have enjoyed it quite a bit. I would love to see you discuss gaming and how some of the newer tech is built. Like for example what is a Cuda Core exactly and how are they built?
Awesome explanation Gary! Seeing the 68000 views this video currently has reminded me of the Motorola 68k introduced in 1979, which was named as such because it had 68000 transistors, and was a chip used by things like the Sega Genesis, Amiga, Apple and NEXT systems well into the mid 90s. It was considered high end at the time, but pales heavily in comparison to today's microprocessors! Pretty incredible to think that we're now at billions of transistors some 40 years on, a 14000x increase!! And in systems that run on a small battery and fits in your pocket, no less!
Great video. It amazes me that, with the costs you have described, I can buy a packaged multi-core microcontroller chip for less than a dollar. The smaller chips we're playing with at home are remarkable value.
I do enjoy this channel, you're very good at covering these topics. You have a tendency to rudely and aggressively jump down your subscribers' throats the moment they show any misunderstanding or misconception of the highly complex topics being discussed but your screen persona is polite at least and you do know your stuff.
How dare you... I'll show you... LOL, only kidding 😂😜 If I analyze myself, which I know can be hard, I don't have a problem with people misunderstanding things. I wouldn't make these videos, if I did. I struggle with people who make it personal, and start calling me names or make personal remarks about me. Also with people who have a little bit of knowledge and think they know everything. When I then ask them to prove or explain or expound they tend to get belligerent. There seems to be universal imbalance with RUclips. It seems the rule is that viewers can write whatever they want and the video creator must just accept it, but if the creator replies then some how I am being rude. I don't think I am just rude for the sake of it, well I hope I am not, I think, as I said, there is an imbalance in attitude. No one ever said, go read the comments section on RUclips it is so nice there.
@@GaryExplains Right, that's it, I demand satisfaction! Pistols at dawn! Jokes aside, people who are trolling / just rude / arrogant in general deserve a bit of a dressing down and you've got every right to. That's not what I was referring to. I was referring to people who simply get something wrong, haven't understood and maybe ask a bit of a dumb question - but do it politely. I mean, I've yet to see a case where they were right and you weren't but jumping down their throat and saying words to the effect of "did you watch the video or not?!" Well, clearly they did and just didn't understand it... If you're discussing highly technical details about chipsets or whatever, it might seem obvious to you and me, but some lay people might struggle / misunderstand and ask a dumb question or say something that's plainly wrong. That sort of person isn't a troll, they haven't been rude or claimed to be an expert (yet, at least) it's an opportunity for them to learn. Jumping down the throat of someone like that because they made a mistake is a bit unedifying. That's a reservation I have but, on balance, I very much like the channel and appreciate what you do.
Hmmm. I understand what you are saying, but politely I disagree. Many times when I ask people if they watched the video, I would say 8/10, if the person replies they admit that they didn't and they were just commenting based on the title or the first couple of minutes. I don't recall any situations where I have replied unkindly to a genuine question from someone who actually watched the video but didn't get something. In my defense I remember lots of people who thanked me for interacting and helping them clear up any doubts or misunderstandings. Maybe you could point me to some examples, worse case it will help me to see the error of my ways.
@@GaryExplains Oh goodness Gary, I'll not going to go through comments looking for unpleasant exchanges. I appreciate you taking my comments on board and responding to me. That aside, this channel is an absolute credit to you. Your enthusiasm and expertise are simply brilliant and wish you every success.
Indeed there are lots of comments, that is also one reason why some of my replies can seem terse at times, as I am literally reading thousands of comments. But here is any example of someone who liked my replies: ruclips.net/video/Fi0AKrprWxg/видео.html&lc=UgwDNYfAQJnW3jJvKuh4AaABAg
As an RF/mmWave graduate student I design MMICs so I’m somewhat familiar with some of these processes, but it still blows my mind the way the foundries are able to etch to sub micron level resolution.
Those dies are not finished yet. Later on they will be covered with a lot of copper and μBumps will be made if flip-chip technology will be used. You saw the wrong side of a die, but other side still has protected layer that you can remove with small grid sand paper.
You did a good job on this, but you showed mosfets cross sections, and bipolar transistor schematics. Since the logic circuits are quite a bit different(and they are mostly mosfets in modern cpu designs), you should try to fix that if you can :) Also an interesting related topic is power use is mostly switching speed, as the state of the nodes change, it is mostly just charging and discharging gate and interconnect capacitance. Which is why power use is so related to clock speed and cooling is dependent on Watts/chip area. Cray Research estimated you could air cool 100W/sq inch, and 200 for liquid cooling.
I decided to nitpick the nitpickers. :-) The transistors are P and N CMOS transistors. NMs are 2D measurements. Could the 7nm ??? be from a third a third dimension?
Thanks Gary! This is a awesome video that only you could do! Thanks for the video! LLAP BTW love the music. Feels like I'm watching a episode of 'This Old House" ... :-)
great explanation but I was really hoping to see a little more detail. I know we can't just get random videos inside intel and AMD but I was kinda hoping for something more visual. However, this is one of the best explanations I've seen, sending to my nephews to let them see and learn. Thanks Gary
Because most of the processing is done inside machines, you won't see much. The few clips he did show is a good representation of the entire process overall; just wafers being loaded into hundreds of different machines. You should be able to look up all the different steps and get a detailed understanding of each process, but to do that in a single video would be hours long.
21:45 Do they get close to 100% yield from the wafers nowadays? I remember reading (back in the 80's) yields were around 33% so the majority of chips on the wafer were useless junk. Some could be "salvaged" by either down-clocking, or disabling functionality (AMD did this with the 29000. If the MMU or Branch Target Cache failed, they'd sell the chip as a 29005 which had neither). If they really usually get full yields out of the wafers, that really shows how far things have come along.
I would be surprised if they did. I did yield analysis in the 80's, and for manufacturing yield it was mostly broken into photo resist flaws, and contamination. For the new fabs they constructed, they would not hire smokers for any fab jobs, no perfumes, anything that smelled was not allowed in the clean rooms. more rarely there were missed layers, and other stupid stuff, those everything failed. And you're right about slower clocks, but there might not have even been a cpu designed without the MMU or cache, that would probably be a sales vs yield trade off.
Not at all, a 100% is almost impossible to get. For new technologies though, a 60% yield is seen as quite problematic, so depending on the node you want to be in the 80% range. Another thing is that yield is not only determined by the foundry processes but also by the design. There are DFM rules that have different levels of priority and if followed will increase the yield of the circuit. But these come with tradeoffs so not always do you want to follow all these recommended rules (for example you may increase the area usage or affect the bandwidth of your design if you follow them).
People were always the major causes of contamination in a cleanroom. In modern fabs, people have mostly been eliminated from the process core and the wafers move automatically from process to process. However, line width has also shrunken so now much smaller pieces of foreign material will cause problems. It would be very surprising if the yield was 100%. It could very well be 80/90% though.
@@GaryExplains that’s awesome Gary , if possible I would love you to do videos breaking down a die shot of something like the 888. I haven’t been able to find a shot of it or the die size anywhere. I want to do so to try and get an idea of Samsung’s 5nm lpe
While something like that would be great, I don't have access to any special/secret information. If you can't find a shot of it then probably I can't either. It looks like Tech Insights has some die shots, but you need to pay for them: www.techinsights.com/products/ace-2101-801
im interested in how often the asml machines fail or what the life cycle of one is what kind of maintenance to expect and costs associated with that does anyone know or have a good guess?
Well, it will be quite a while before one shows up on eBay. A large number of the billions of chips that are made are on the mature (older) process nodes. These machines are always in high demand.
I think that maybe I covered that enough in videos like Arm vs x86, or Arm vs RISC-V. If you have watched those and you think there is still some gaps that I need to fill then please let me know.
Sir it becomes so hard to even imagine the steps that goes through churning a microscopic transistor from a CD type silicon wafer...what happens to those Dutch machines after the process node becomes outdated? Do they make new machines for different process nodes, if yes then is there any use for like 28nm machines in todays time sir?
Nicely summarized and in under 30 mimutes. It was important to comment on the RISC-V hype. Unless they have access to a huge amount of near obsolete manufacturing capacity it is not going to be cheap to manufacture. And good luck competing with the Automotive Industry for that capacity. Generally, these type of manufacturing processes have limited capacity, so there won't be much of a revolution if you cannot supply enough of the chips. And you are not going to threaten the hegemony with processors that are order of magnatude slower. They would need to use that same, very expensive, Process Nodes as the leasding processors.
So now that we know how a Processor/SoC/GPU is made per se, how does the processor actually crunch data. Because basically the processor is processing billions of 1' and 0's and how does that translate to what we see on the screen.
When the transistor density doubles then the process node takes the name that is 0.7 of the previous one. For the other nodes like 12, 8, 6nm etc, these are process node where the density has been increased, but not doubled.
Thank you for the clear explanation, Gary. But I have question, how intel or amd classified chips for example i3, i5, i7? Do they make separate litography for each?
Yes and no. Every processor has its own mask and unique lithography, but to save costs companies like Intel or AMD will often use the same physical chip for several models and physically disable a feature while leaving it on the die. They also test all the chips and the ones that can't run at the highest clock speeds are sold as slower models in the range. For example the difference between the Intel Core i5-1130G7 and the Intel Core i5-1135G7 is that one runs as 4GHz (Max) and the other 4.2GHz (Max). Same chip.
@@GaryExplains it seems to me that it would be wasteful to intentionally make an i3, i5, and i7. It seems likely that Intel starts out trying to make only the fastest i7s and the natural manufacturing process creates the i5s and i3s. Thus there is no such thing as an i3, but instead it is a defective i7.
@@mdrew44628 No, you are confusing "binning" where a 2.5GHz processor might really just be a failed 2.7GHz processor, but that is about the limit to it. Certainly not the case that an i3 is just a defective i7, no. Sorry.
@@GaryExplains well I was looking at it this way. If you used the same die size for the i3, i5, and i7 and they went through the same process, why would you purposely disable certain features like number of cores, RAM cashe size, etc. and then charge a lower price for a chip that cost the same to manufacture. If you look at the topology of the wafer, foreign material is going to pepper the surface during processing and will create bad i7s. Instead of discarding these bad i7s, if you had a good design, you could simply disable the bad parts of the chip and call it an i5 or i3. That way you end up with 90% total yield on each wafer instead of only 45%.
As transistors and logic gates are getting closer and closer to the size of the silicon atom, do you not think it’s making the work Xanadu and quantum computing more viable? Then we can start again making them smaller and smaller.
Note that masks are only over a million dollars for the leading-edge stuff. For really old processes (well over 100nm) the mask sets might only be tens of thousands of dollars. Obviously the higher resolution needed for the smaller geometries are reflected by the higher resolution needed for the mask set. Larger geometries are MUCH easier to make. Larger geometries are also more refined (years of practice making wafers) so the yields are better, and the machines have largely been paid for over the years. As you go to smaller process nodes, you also need more expensive EDA tools. Cadence sells an "advanced node" license that you need on top of the license to use the layout tool. Once you need to factor in the wavelength of light, the mask sets can start to look more like diffraction gratings (not that I have any personal experience in anything so small), so the tool makers want more money to turn on such features. But if you are making something that is pad-limited (the number of IO pads put a limit on how small the die can be), then you can either put more transistors in the core area (add features, memory, etc.), or you can just use larger transistors to save a few bucks.
ARM supply (sell) the design for the main processor core (think of it as a blueprint for an engine). Qualcomm then bolt on their extra hardware into this blueprint (Modems, GPUs, etc). TSMC would then be the one to turn Qualcomms blueprint into a physical chip.
Yeah, I know. Sorry about that. Several others have pointed that out. But if that is all there is to complain about in a 25 minute video on a complex subject then I am happy.
It brings back some almost forgotten memories. Around 1991 I worked for 6 years in the Waferfab Automation Department of Philips Semi Conductors Industry in Nijmegen, now Nexperia-ITEC. In that time we had a lot of contacts with the Philips Research Lab and AMSL a former part of Philips both in Eindhoven. A colleague went for 1 year to TMSC Taiwan. I lived in interesting times!
Now we have super computer in our pockets, and people still complain about it's not fast enough.
Gary is the best at explaining complicated stuff in an understandable way!
The Professor professes very well!
But he should have explained the MOSFET instead of a PNP or NPN transistor, 'cos it's commonly used in CPUs
@@1MarkKeller 6
@@dejangavrilov6459 Classmate!
Man no other RUclipsr can cover the topics you do truly an unique chanel
The Professor is a proficient professer!
Dr. Ian Cutress from Tech Tech Potato has a similar channel. There are people who can cover this subject but arent as big so you're not aware of them.
@@JayHere I follow him bro de doesn't do animation though
My main question here being -
Even if you can control semiconductor like if it can conduct or not [9:40], it's done when current is passed through it or not. But a conductor by definition is something which conducts WHEN current is passed through it.. so isn't semiconductor just a conductor at all times except when it's not doing anything in which case, it shouldn't even matter if it's conductor or not
Gary explained everything tech....
Thank you so much for making these videos. I find the whole idea of mobile phones and laptops so fascinating due to how much they’re able to do, but I’ve never understood how they were able to work. With Apple releasing the M1 chip I’ve become more interested in learning about it and your videos are really good at explaining the basics. I still find myself getting a bit lost with some of the more technical terms but I usually look them up if I’m not feeling too lazy haha.
19:13 Semiconductor chips are one of the most precisely engineered things we see in daily life. Imagine how well-engineered and precise the machines that make the chips need to be.
I had no idea of the complexities involved in the manufacture of a cpu. It certainly makes you realize the things we take for granted! An amazing video! Thank you Gary!
Facinating video Gary! Thanks!
Very, very interesting informations and explanations. I really din't know the difference of numbers of transistors in a lithography type, amongst the manufacturing companies. I thought it was a standard thing! Thanks for all the efford and research!
I know there wasn't time to go into much detail about transistors, but in 9:08 the symbol on the left is for a bipolar junction transistor (BJT), while the illustration on the right is of a field effect transistor (FET). These are different designs. In particular, the FET is a voltage-driven device. There's a *voltage* applied to the middle pin, but it doesn't result in any *current* flowing to or from the middle pin.
A really cool elaboration on this design is to leave a disconnected gate in a FET, and then you get flash memory.
Yes, I know I used the wrong symbol. Sorry. You aren't the first person to point it out
Thanks for the beautiful explanation Gary 👏👏
A great video Gary - Excellent summary about making modern CPUs - very compact but never the less extremely extensive content. I was kind of shocked that all big CPU manufactures TSMC, Samsung and even Intel are dependent on just one company worldwide that is able to produce these extreme ultra violet lithography machines. It's the ASML Holding (en.wikipedia.org/wiki/ASML_Holding) in the Netherlands NOT Denmark. In other words, the hole 'silicon' world depends on just one single point of failure. This is quite scary to me.
The world is a complicated place. Apple and Samsung are obviously competitors, so I was blown away when I learned that Samsung made the screen for the iPhone X. As we have learned in the last year, global supply chains are highly integrated and optimized for regular flow, meaning any disturbances propagate all over.
This is a great short explanation, Gary!
Very good job, Gary!👍👍
Thank you! Cheers!
Wow! Been looking for this info for so long. Thank you! Now to find how cpu cache and instructions work and how it’s implemented in these tiny transistors
I have some videos on how CPUs work plus a video about cache memory.
@@GaryExplains Cool! Just came across this video out of the blue and subbed after watching it. Will check it out when I get home. Thank you!
Thanks Gary, that’s beyond academic grade education. Your way of articulating the info for your topics could land to a degree. I don’t know how up to date Intel’s finfet is, but a comparison to their processes with the ASML machine would be awesome to learn.
FinFet has been the standard for all chips, however to make chips smaller this will need to be replaced with GAA = Gate All around.
This however has more to do with chip design, not so much with the ASML machine.
Love the way how Gary get excited when talk about this topics. Great mate!
Thanks for watching!
Thank you for explaning the works of the transistors
Thank you professor for explaining!
This is very interesting and I have enjoyed it quite a bit. I would love to see you discuss gaming and how some of the newer tech is built. Like for example what is a Cuda Core exactly and how are they built?
This was necessary🙌🏻
I am glad it was helpful.
Awesome explanation Gary! Seeing the 68000 views this video currently has reminded me of the Motorola 68k introduced in 1979, which was named as such because it had 68000 transistors, and was a chip used by things like the Sega Genesis, Amiga, Apple and NEXT systems well into the mid 90s. It was considered high end at the time, but pales heavily in comparison to today's microprocessors! Pretty incredible to think that we're now at billions of transistors some 40 years on, a 14000x increase!! And in systems that run on a small battery and fits in your pocket, no less!
Great video. It amazes me that, with the costs you have described, I can buy a packaged multi-core microcontroller chip for less than a dollar. The smaller chips we're playing with at home are remarkable value.
I do enjoy this channel, you're very good at covering these topics. You have a tendency to rudely and aggressively jump down your subscribers' throats the moment they show any misunderstanding or misconception of the highly complex topics being discussed but your screen persona is polite at least and you do know your stuff.
How dare you... I'll show you... LOL, only kidding 😂😜 If I analyze myself, which I know can be hard, I don't have a problem with people misunderstanding things. I wouldn't make these videos, if I did. I struggle with people who make it personal, and start calling me names or make personal remarks about me. Also with people who have a little bit of knowledge and think they know everything. When I then ask them to prove or explain or expound they tend to get belligerent. There seems to be universal imbalance with RUclips. It seems the rule is that viewers can write whatever they want and the video creator must just accept it, but if the creator replies then some how I am being rude. I don't think I am just rude for the sake of it, well I hope I am not, I think, as I said, there is an imbalance in attitude. No one ever said, go read the comments section on RUclips it is so nice there.
@@GaryExplains Right, that's it, I demand satisfaction! Pistols at dawn!
Jokes aside, people who are trolling / just rude / arrogant in general deserve a bit of a dressing down and you've got every right to.
That's not what I was referring to. I was referring to people who simply get something wrong, haven't understood and maybe ask a bit of a dumb question - but do it politely. I mean, I've yet to see a case where they were right and you weren't but jumping down their throat and saying words to the effect of "did you watch the video or not?!" Well, clearly they did and just didn't understand it... If you're discussing highly technical details about chipsets or whatever, it might seem obvious to you and me, but some lay people might struggle / misunderstand and ask a dumb question or say something that's plainly wrong.
That sort of person isn't a troll, they haven't been rude or claimed to be an expert (yet, at least) it's an opportunity for them to learn. Jumping down the throat of someone like that because they made a mistake is a bit unedifying.
That's a reservation I have but, on balance, I very much like the channel and appreciate what you do.
Hmmm. I understand what you are saying, but politely I disagree. Many times when I ask people if they watched the video, I would say 8/10, if the person replies they admit that they didn't and they were just commenting based on the title or the first couple of minutes. I don't recall any situations where I have replied unkindly to a genuine question from someone who actually watched the video but didn't get something. In my defense I remember lots of people who thanked me for interacting and helping them clear up any doubts or misunderstandings. Maybe you could point me to some examples, worse case it will help me to see the error of my ways.
@@GaryExplains Oh goodness Gary, I'll not going to go through comments looking for unpleasant exchanges.
I appreciate you taking my comments on board and responding to me. That aside, this channel is an absolute credit to you. Your enthusiasm and expertise are simply brilliant and wish you every success.
Indeed there are lots of comments, that is also one reason why some of my replies can seem terse at times, as I am literally reading thousands of comments. But here is any example of someone who liked my replies: ruclips.net/video/Fi0AKrprWxg/видео.html&lc=UgwDNYfAQJnW3jJvKuh4AaABAg
Gary, thank you for N-type and P-type semiconductors and logic. I had almost imagined this.
I enjoyed this video, Gary you are really 5nm, billions of transistors, you are the best!!!!!!!!
13:45 I will remember that chartch. THANKS Gary!!!!!!!!
As an RF/mmWave graduate student I design MMICs so I’m somewhat familiar with some of these processes, but it still blows my mind the way the foundries are able to etch to sub micron level resolution.
Love it. Best explanation ever
Thank you
Glad you enjoyed it!
This was very well done.
Amazing explanation...! Got to know so much about manufacturing.
Thank you.
Amazing stuff Garry!!!!
Great job, man that has to be the best video on the topic on all of RUclips!
You clearly haven’t watched “silicon run“ then
How are those colourful images of dies (die shots) taken?
Delided CPUs usually looks just quite opaque black slab
Those dies are not finished yet. Later on they will be covered with a lot of copper and μBumps will be made if flip-chip technology will be used. You saw the wrong side of a die, but other side still has protected layer that you can remove with small grid sand paper.
Aren't they just diagrams or false-colour or something?
Actually never mind, I think voytechj is right
Gary,
You explained!
You did a good job on this, but you showed mosfets cross sections, and bipolar transistor schematics. Since the logic circuits are quite a bit different(and they are mostly mosfets in modern cpu designs), you should try to fix that if you can :) Also an interesting related topic is power use is mostly switching speed, as the state of the nodes change, it is mostly just charging and discharging gate and interconnect capacitance. Which is why power use is so related to clock speed and cooling is dependent on Watts/chip area. Cray Research estimated you could air cool 100W/sq inch, and 200 for liquid cooling.
A brilliant and informative video Gary. Excellent!! Well done. You explained it really well. Looking forward to seeing you in the next one. 😊
woooow great explanation for a very complicated topic in such a beautiful and understandable way
Great video Gary
Good info. Nicely explained.
Thank you!
great video... superbly explained! Unbelievable what we can create nowadays!
I decided to nitpick the nitpickers. :-) The transistors are P and N CMOS transistors. NMs are 2D measurements. Could the 7nm ??? be from a third a third dimension?
Love your videos... this one was especially interresting 👍
9:28 the picture on the right shows an n-channel mosfet
Yes, I made a mistake. You aren't the first person to point it out.
Thanks Gary! This is a awesome video that only you could do!
Thanks for the video!
LLAP
BTW love the music. Feels like I'm watching a episode of 'This Old House" ... :-)
lol, true!
Great video very well explained
Very interesting info! Thanks a lot
My pleasure!
Thank you prof, it reminds me of my year in universities!!
best explanations for this field I have ever come across. Cheers, Gary
That was great, excellent explanation. Very informative.
This did a pretty amazing explanation for a 25 minute video, although ISAs weren't touched upon as much.
That was extremely interesting. Thanks!
Gary you do explain no doubt that's why love ur contents always
great explanation but I was really hoping to see a little more detail. I know we can't just get random videos inside intel and AMD but I was kinda hoping for something more visual. However, this is one of the best explanations I've seen, sending to my nephews to let them see and learn. Thanks Gary
Because most of the processing is done inside machines, you won't see much. The few clips he did show is a good representation of the entire process overall; just wafers being loaded into hundreds of different machines. You should be able to look up all the different steps and get a detailed understanding of each process, but to do that in a single video would be hours long.
21:45 Do they get close to 100% yield from the wafers nowadays? I remember reading (back in the 80's) yields were around 33% so the majority of chips on the wafer were useless junk. Some could be "salvaged" by either down-clocking, or disabling functionality (AMD did this with the 29000. If the MMU or Branch Target Cache failed, they'd sell the chip as a 29005 which had neither). If they really usually get full yields out of the wafers, that really shows how far things have come along.
I would be surprised if they did. I did yield analysis in the 80's, and for manufacturing yield it was mostly broken into photo resist flaws, and contamination. For the new fabs they constructed, they would not hire smokers for any fab jobs, no perfumes, anything that smelled was not allowed in the clean rooms. more rarely there were missed layers, and other stupid stuff, those everything failed. And you're right about slower clocks, but there might not have even been a cpu designed without the MMU or cache, that would probably be a sales vs yield trade off.
Not at all, a 100% is almost impossible to get. For new technologies though, a 60% yield is seen as quite problematic, so depending on the node you want to be in the 80% range.
Another thing is that yield is not only determined by the foundry processes but also by the design. There are DFM rules that have different levels of priority and if followed will increase the yield of the circuit. But these come with tradeoffs so not always do you want to follow all these recommended rules (for example you may increase the area usage or affect the bandwidth of your design if you follow them).
People were always the major causes of contamination in a cleanroom. In modern fabs, people have mostly been eliminated from the process core and the wafers move automatically from process to process. However, line width has also shrunken so now much smaller pieces of foreign material will cause problems. It would be very surprising if the yield was 100%. It could very well be 80/90% though.
This was amazing thank you!
So if a cpu has say 2 cores that have failed, does the manufacture label it as a lesser chip?
I’ve always loved deep tech dives like this , my inner geek is unleashed lol. How did you learn all this your self Gary? University or self taught
I have a computer science related honors degree plus I was a professional software engineer for 10+ years. But I do a lot of research for every video.
@@GaryExplains that’s awesome Gary , if possible I would love you to do videos breaking down a die shot of something like the 888. I haven’t been able to find a shot of it or the die size anywhere. I want to do so to try and get an idea of Samsung’s 5nm lpe
While something like that would be great, I don't have access to any special/secret information. If you can't find a shot of it then probably I can't either. It looks like Tech Insights has some die shots, but you need to pay for them: www.techinsights.com/products/ace-2101-801
@@GaryExplains thanks so much Gary , best wishes from the USA
OMGAWD. Thanks 🙏 for the vid.
There are also the EDA companies like Cadence,Synopsys,Mentor Graphics , which makes the software for the designing the chip.
im interested in how often the asml machines fail or what the life cycle of one is what kind of maintenance to expect and costs associated with that does anyone know or have a good guess?
Ultra UV lithography, wow what a machine, would like to see @MikesElectricStuff do a tear down 😄👍
Well, it will be quite a while before one shows up on eBay. A large number of the billions of chips that are made are on the mature (older) process nodes. These machines are always in high demand.
Nope we were way past UV lithography a decade ago. 10nm is the wavelength for near X-rays and we have chips these days in the lab working at 2nm.
Fantastic video, thank you! Could you please make a footage about ARM's role in this process?
I think that maybe I covered that enough in videos like Arm vs x86, or Arm vs RISC-V. If you have watched those and you think there is still some gaps that I need to fill then please let me know.
Nicely explained
Photonic Chip looks to be a thriller in the making.
Good work, very high level but a good overview.
Great video, thanks!
A1 explanation thank you👍👍👍
Unfortunately there will be a delay of a few years for the delivery of high NA EUV Maschines from ASML. So they have to use multi pattering for EUV. 😢
*GARY!!!*
Good afternoon Professor!
Good afternoon fellow classmates!
MARK!!!
Thanks. Very simple to learn for people who've heard basic terms before
This is the explanation we NEED
Man. This video is just amazing 👏 👍👌
thanks Gary this helps and enlighten me
@9:23 Nitpick alert! The symbol is for a bipolar junction transistor, the picture is of a MOSFET. MOSFET symbol is different.
Yeah, several other people have made the same nitpick. My bad. I have already beaten myself so that I don't make the same mistake again.
Sir it becomes so hard to even imagine the steps that goes through churning a microscopic transistor from a CD type silicon wafer...what happens to those Dutch machines after the process node becomes outdated? Do they make new machines for different process nodes, if yes then is there any use for like 28nm machines in todays time sir?
They tend to keep being used for older designs if they are still in production.
Amazing video. Thanks a lot.
Do you think EUV lithography will reach the same numeric aperture as DUV lithography. Like 1 or even 1.3 as it was use in submersive DUV lithography?
Nicely summarized and in under 30 mimutes.
It was important to comment on the RISC-V hype. Unless they have access to a huge amount of near obsolete manufacturing capacity it is not going to be cheap to manufacture. And good luck competing with the Automotive Industry for that capacity. Generally, these type of manufacturing processes have limited capacity, so there won't be much of a revolution if you cannot supply enough of the chips. And you are not going to threaten the hegemony with processors that are order of magnatude slower.
They would need to use that same, very expensive, Process Nodes as the leasding processors.
Is each layer another physical wafer or something etched at another depth in one wafer?
Awesome, excellent info.
So now that we know how a Processor/SoC/GPU is made per se, how does the processor actually crunch data.
Because basically the processor is processing billions of 1' and 0's and how does that translate to what we see on the screen.
That was a nice refresher...
Very well explained. Are you an electronic engineer?
No, my training and experience is more software, but I try my best with the hardware stuff.
@@GaryExplains great work and well explained. You have a special gift
Very kind of you. Thx.
can you explain how are there 12, 8, 6 nm nodes
It's basically the track width and those sort of sizes use X-ray lithography.
When the transistor density doubles then the process node takes the name that is 0.7 of the previous one. For the other nodes like 12, 8, 6nm etc, these are process node where the density has been increased, but not doubled.
@@GaryExplains thanks
Props to the guys who services the ASML machines
Excellent video.
Best explanation💯💯
What about battery life? Does a 5 nm processor offer better life than 7nm or is it all just marketing?
What a amazing video congratulations.
Now we know why SD888 kinda sucks with thermals. Hope Qualcomm can secure TSMC slot for its next flagship.
Thank you for the clear explanation, Gary. But I have question, how intel or amd classified chips for example i3, i5, i7? Do they make separate litography for each?
Yes and no. Every processor has its own mask and unique lithography, but to save costs companies like Intel or AMD will often use the same physical chip for several models and physically disable a feature while leaving it on the die. They also test all the chips and the ones that can't run at the highest clock speeds are sold as slower models in the range. For example the difference between the Intel Core i5-1130G7 and the Intel Core i5-1135G7 is that one runs as 4GHz (Max) and the other 4.2GHz (Max). Same chip.
@@GaryExplains it seems to me that it would be wasteful to intentionally make an i3, i5, and i7. It seems likely that Intel starts out trying to make only the fastest i7s and the natural manufacturing process creates the i5s and i3s. Thus there is no such thing as an i3, but instead it is a defective i7.
@@mdrew44628 No, you are confusing "binning" where a 2.5GHz processor might really just be a failed 2.7GHz processor, but that is about the limit to it. Certainly not the case that an i3 is just a defective i7, no. Sorry.
@@GaryExplains well I was looking at it this way. If you used the same die size for the i3, i5, and i7 and they went through the same process, why would you purposely disable certain features like number of cores, RAM cashe size, etc. and then charge a lower price for a chip that cost the same to manufacture. If you look at the topology of the wafer, foreign material is going to pepper the surface during processing and will create bad i7s. Instead of discarding these bad i7s, if you had a good design, you could simply disable the bad parts of the chip and call it an i5 or i3. That way you end up with 90% total yield on each wafer instead of only 45%.
Enjoyable content. Thank you very much!
Glad you enjoyed it!
As transistors and logic gates are getting closer and closer to the size of the silicon atom, do you not think it’s making the work Xanadu and quantum computing more viable? Then we can start again making them smaller and smaller.
Note that masks are only over a million dollars for the leading-edge stuff. For really old processes (well over 100nm) the mask sets might only be tens of thousands of dollars. Obviously the higher resolution needed for the smaller geometries are reflected by the higher resolution needed for the mask set. Larger geometries are MUCH easier to make.
Larger geometries are also more refined (years of practice making wafers) so the yields are better, and the machines have largely been paid for over the years.
As you go to smaller process nodes, you also need more expensive EDA tools. Cadence sells an "advanced node" license that you need on top of the license to use the layout tool. Once you need to factor in the wavelength of light, the mask sets can start to look more like diffraction gratings (not that I have any personal experience in anything so small), so the tool makers want more money to turn on such features.
But if you are making something that is pad-limited (the number of IO pads put a limit on how small the die can be), then you can either put more transistors in the core area (add features, memory, etc.), or you can just use larger transistors to save a few bucks.
Outstanding! 👍
Glad you liked it!
I am a bit confused. Say Qualcomm designs a chipset and TSMC produces it, what is the role of ARM in it and their Cortex A53, 57, 77 etc series CPUs??
ARM supply (sell) the design for the main processor core (think of it as a blueprint for an engine). Qualcomm then bolt on their extra hardware into this blueprint (Modems, GPUs, etc). TSMC would then be the one to turn Qualcomms blueprint into a physical chip.
@@SerBallister isn't Mali also developed by ARM??
@@ashishnmbr yeah, that's an optional license
@@SerBallister cool.. thanks for clarifying
Thank you, professor.
I learnt so much from this channel. 😄👍🏼
Happy to hear that!
Gary, review your technical explanations, you presented a MOS transistor structure, but a BIPOLAR transistor diagram.
Yeah, I know. Sorry about that. Several others have pointed that out. But if that is all there is to complain about in a 25 minute video on a complex subject then I am happy.