I'm doing this right now in A level I.C.T in Computer Architecture, and I can't say this enough: Thank you!! Your video is the most simple and well explained one I've been able to find and actually understand! :D
He is merely telling what happens and how it happens. He does not explain why this is the way things are done. How are you supposed to remember anything without being able to develop clear context?
Well if the teacher had to explain why everything you learn about was designed the particular way it was, it would become pretty time consuming and I dont think anyone would have enough time to finish learning all the course content.
Thank you sir, I have been going through a lots of videos, diagrams, notes, etc etc, But this is the most simplest one i came across, this is gonna solve a lot of my problems, Thanks a lot. My only question, Is that the RAM you are referring as Main store?
Nice explanation. I have a doubt: How does the decode works on the LDA 110, Like how does CIR knows if the its is a instruction register or a another memory register (110) that needs to put the value in it. Example 1: LDA #1 -> 1 was the value in accumulator Example 2: LDA 110 ---> 110 is the address, takes the value at the address 110 i.e 150 Could you please elobrate, quite confuse at that point?
The CIR contains the opcode which states the instruction following this is the effective address mode which tells the CU how to interpret the operand part. Assembly language uses notations to indicate the addressing modes. e.g. let's say the opcode for LDA is 01101 the next three bits could be used for the addressing mode and the next 8 bits for the operand (this is just made up no particular cpu here) opcode ea operand 01101 001 1100 0010 LDA #10 - immediate 10 is the value to load - instruction in machine code 01101 000 0000 1010 LDA 10 - load value from address 10 - instruction in machine code 01101 001 0000 1010 LDA (10) - load address 10 and load value at this address - instruction in machine code 01101 010 0000 1010 hope the formatting is ok
+HurrayBannana Something is really annoys me when you explain the halt. When talking about all other operation you said that it increases the program counter then checks for interruptions. Should it not do this for the halt command and if not why.
when it decodes the halt it needs to increment so the pc is pointing to the next instruction to execute, if it didn't do this when it returns from the interrupt that breaks the CPU out the halt operation it would re-execute the halt rather than proceed with the program e.g. (taken from some pacman hardware coding I have done). So below when processing has finished for the frame I issue a halt, which sits there until the vsync interrupt occurs which does various frame based procesing, when this interrupt finishes we need to execute the jump instruction and start the loop again. mainloop: ld a,(mode) ;get mode cp title_mode ;is it title mode jp z,title_logic ;yes cp game_mode ;is it game mode jp z,game_logic ;yes cp game_over ;is it game over jp z,game_over_logic ;yes wait: halt ;finished processing let's wait for vsync jp mainloop ;perform logic again
as the data held is assumed to be an instruction. it will hold a bit pattern containing three items (not all instructions require ooerands or addressing modes) an opcode (1), an effective addressing mode (2) to determine how the operand (3) should be used to determine the effective address of the data for the instruction
Your Students are damn lucky to have a Teacher like you .
Thank you! I'm doing my As-level right now and this was the only topic that I could not understand. You have explained it well! thanks again!
I'm doing this in my first year of GCSE in Northern Ireland, since all of the courses are now AS level. Thanks government!
I keep coming back to this video it is a perfect explanation.
thanks, tried to keep it simple but explain the process rather than get bogged down with latches and enables and the like
I'm doing this right now in A level I.C.T in Computer Architecture, and I can't say this enough: Thank you!! Your video is the most simple and well explained one I've been able to find and actually understand! :D
no problem, happy to have helped
Great teacher your students are lucky to have you!
He is merely telling what happens and how it happens. He does not explain why this is the way things are done. How are you supposed to remember anything without being able to develop clear context?
Well if the teacher had to explain why everything you learn about was designed the particular way it was, it would become pretty time consuming and I dont think anyone would have enough time to finish learning all the course content.
Good tutorial m8, Gabe shines his light down upon you
Please, grow up.
Thank you. Great teacher!
This video helped me more than my actual teacher even though I study in French
Obito Uchiha glad it helped
haha
Thank you so much for this upload! I'm currently doing my HNC in Scotland and this is going to help me out so much come exam times!
no problem
Hi Liam ... :)
great video, this has helped me out loads for an assignment
Thank you so much, I didn't understand this during my lesson, but this helped a lot.
This is top-notch, I just wished that you tilted the camera slightly to the left so I could see the side-notes, but I can cope with it. Thank you.
Yeah sorry about that
it was just the fetch execute steps
pc to mar
ms [ mar ] to mdr
mdr to cir
increment pc
decode
execute
check for interrupts
HurrayBanana Thank you so much! A life-saver! Don't worry, I knew what was going on, I just wanted to make sure that I am following the same steps.
This was crazy informative.
glad to have helped
Yes Adham great lives think alike
Is there another video i can find on youtube or the internet that has a similar setup yet covers things in much greater and deeper detail?
Solid work, very impressive.
Nice one mate! This is really going to help tomorrow!
Thanks so much! Never understood this shit until now.
Can't see the writings on the left side :(
Great stuff! Very instructive.
Thanks this was really helpful
I agree.
Thank you for the tutorial, now I know what time the coffee shop opens on a sundayy lmao
Great Video! Thanks for the help :)
What about the immediate access store? What role does that play in the fetch execute cycle?
Yhe that is good i can understand really thanks indeed
Really good. Thanks...
Thank you sir,
I have been going through a lots of videos, diagrams, notes, etc etc,
But this is the most simplest one i came across,
this is gonna solve a lot of my problems,
Thanks a lot.
My only question, Is that the RAM you are referring as Main store?
From keyboard to MAR , is there an encoder and decoder? Thanks
Thanks, that helped a lot!
Also thank you this was so helpful
Nice explanation. I have a doubt:
How does the decode works on the LDA 110, Like how does CIR knows if the its is a instruction register or a another memory register (110) that needs to put the value in it.
Example 1: LDA #1 -> 1 was the value in accumulator
Example 2: LDA 110 ---> 110 is the address, takes the value at the address 110 i.e 150
Could you please elobrate, quite confuse at that point?
The CIR contains the opcode which states the instruction following this is the effective address mode which tells the CU how to interpret the operand part. Assembly language uses notations to indicate the addressing modes.
e.g.
let's say the opcode for LDA is 01101 the next three bits could be used for the addressing mode and the next 8 bits for the operand (this is just made up no particular cpu here)
opcode ea operand
01101 001 1100 0010
LDA #10 - immediate 10 is the value to load - instruction in machine code 01101 000 0000 1010
LDA 10 - load value from address 10 - instruction in machine code 01101 001 0000 1010
LDA (10) - load address 10 and load value at this address - instruction in machine code 01101 010 0000 1010
hope the formatting is ok
Thanks for the prompt reply. So in conclusion, CU decides where it is an direct value, or an address from which value to be loaded. Am i right?
yeah pretty much some bits in the instruction tell it how to calculate the address from the operand
Cool Thanks. Great Explanation.
Does any one out there know how i can or where to go to join this class.?, Please send me an email thank you........
thank u so much
Great stuff. But isn't the PC increment right after a fetch?
+RJduckyard Yes, the PC increment is after the Fetch :)
left part of the white board (i.e., Instruction part) not visible clearly.
But a good video tutorial.
+HurrayBannana Something is really annoys me when you explain the halt. When talking about all other operation you said that it increases the program counter then checks for interruptions. Should it not do this for the halt command and if not why.
when it decodes the halt it needs to increment so the pc is pointing to the next instruction to execute, if it didn't do this when it returns from the interrupt that breaks the CPU out the halt operation it would re-execute the halt rather than proceed with the program e.g. (taken from some pacman hardware coding I have done). So below when processing has finished for the frame I issue a halt, which sits there until the vsync interrupt occurs which does various frame based procesing, when this interrupt finishes we need to execute the jump instruction and start the loop again.
mainloop:
ld a,(mode) ;get mode
cp title_mode ;is it title mode
jp z,title_logic ;yes
cp game_mode ;is it game mode
jp z,game_logic ;yes
cp game_over ;is it game over
jp z,game_over_logic ;yes
wait:
halt ;finished processing let's wait for vsync
jp mainloop ;perform logic again
HurrayBanana oh OK. bit you missed out on saying the increment on the run through with the halt command. This is what confused me.
Now what exactly would this look like with logic gates and flip flops?
There are quite a few YT'rs who have built CPU's from logic circuits
thanks it helped.
Thanks you !!!!!!!!!
Thanks :) !!!!!
Last min revision :D
who is the teacher ? where is this ?
thats what i will like to know.........
WHAT IS THE FULL FORM OF CIR
as the data held is assumed to be an instruction. it will hold a bit pattern containing three items (not all instructions require ooerands or addressing modes) an opcode (1), an effective addressing mode (2) to determine how the operand (3) should be used to determine the effective address of the data for the instruction
thnks..sir
Are you an Australian?
ggs in the chat
Minds*
lol every video on youtube on FEC is made by a british lad
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