One of the last questions wrongly described Adrian Thompson's experiments in evolvable hardware using the old Xilinx XC6200 FPGAs. It was genetic algorithms and not AI. He evolved a circuit that could discriminate between a 1KHz and a 10KHz square wave on its single input by directly mutating the bitfile - no synthesis tools involved. This example was selected between the timing involved is orders of magnitude greater than the delays in the FPGA so it would have to create something like counters at the very least. The evolved circuit was essentially an analog one that no human designer would have created and it wouldn't work if loaded into another FPGA of the exact same model.
Well AI don't mean anything anymore, but genetic algorithms are considered "AI", there are so many different algorithms in machine learning, not everything has to be based on the perceptron model of the neuron to be considered AI. Even simplex optimization can be considered AI nowadays, it really don't mean anything anymore.
I knew a little about what he was talking about, but I didn't want to go too far down the AI/genetic algorithm path as I didn't want to encourage abstracted "tools" which "figure it out for you" as a solution for beginners. New designers who choose such a path don't really get a sense for what is occurring at the RTL level, and when you're first starting out, that can create mysterious problems that are hard to diagnose and debug.
@@monad_tcp I agree. The term "AI" has become incredibly overloaded, to the point that a simple histogram of prior user menu choices in a UI for sorting menu options is now called "AI". As for online AI, the principle of GIGO still applies.
Great talk! While it is generally true that FPGAs don't have internal high impedance, the old Xilinx 4000 family did. It helped not only with busses but also with wide logic like CPLDs can easily implement. But they decided it was better in practice to just stick with multiplexers and never did it again
I remember the XC4000s, but I never used that feature. The automatic timing resolution synthesis tools have abandoned internal tri-state buses in favor of better and faster predictive timing between logic blocks. With the advent of Multi-issue/Multi-transaction silicon backbones (e.g. AXI4), internal tri-states, don't really make sense anymore.
Ha! I hope you got more out of the presentation than that? I have PCB designs going back 40 years, and yes, when they were initially designed (in the US by the way), the standard was in "mils" and a lot of designs that are now vintage were the same (for the US based designs anyway). I currently design in both, depending on the tool and design at hand. Maybe learn how to convert on the fly to handle both?
One of the last questions wrongly described Adrian Thompson's experiments in evolvable hardware using the old Xilinx XC6200 FPGAs. It was genetic algorithms and not AI. He evolved a circuit that could discriminate between a 1KHz and a 10KHz square wave on its single input by directly mutating the bitfile - no synthesis tools involved. This example was selected between the timing involved is orders of magnitude greater than the delays in the FPGA so it would have to create something like counters at the very least. The evolved circuit was essentially an analog one that no human designer would have created and it wouldn't work if loaded into another FPGA of the exact same model.
Well AI don't mean anything anymore, but genetic algorithms are considered "AI", there are so many different algorithms in machine learning, not everything has to be based on the perceptron model of the neuron to be considered AI.
Even simplex optimization can be considered AI nowadays, it really don't mean anything anymore.
I knew a little about what he was talking about, but I didn't want to go too far down the AI/genetic algorithm path as I didn't want to encourage abstracted "tools" which "figure it out for you" as a solution for beginners. New designers who choose such a path don't really get a sense for what is occurring at the RTL level, and when you're first starting out, that can create mysterious problems that are hard to diagnose and debug.
@@monad_tcp I agree. The term "AI" has become incredibly overloaded, to the point that a simple histogram of prior user menu choices in a UI for sorting menu options is now called "AI".
As for online AI, the principle of GIGO still applies.
Great talk! While it is generally true that FPGAs don't have internal high impedance, the old Xilinx 4000 family did. It helped not only with busses but also with wide logic like CPLDs can easily implement. But they decided it was better in practice to just stick with multiplexers and never did it again
I remember the XC4000s, but I never used that feature. The automatic timing resolution synthesis tools have abandoned internal tri-state buses in favor of better and faster predictive timing between logic blocks.
With the advent of Multi-issue/Multi-transaction silicon backbones (e.g. AXI4), internal tri-states, don't really make sense anymore.
And thanks! 😁
'mils'? It is not the dark ages anymore, use standard units of measurement.
Ha! I hope you got more out of the presentation than that? I have PCB designs going back 40 years, and yes, when they were initially designed (in the US by the way), the standard was in "mils" and a lot of designs that are now vintage were the same (for the US based designs anyway). I currently design in both, depending on the tool and design at hand.
Maybe learn how to convert on the fly to handle both?