I am confused at the operation of startup circuit which Rajashekar is describing @ 1:21:37. When the supply is slowly increasing from 0 and still hasn't reached VDD ( 1V or 1.8 ) , how can you assume the gate voltage of M9 to be pulled low? Lets say the Vt of device be 0.7 ( both PMOS and NMOS), then the supply has to be at least 4 Vt for the startup network to work. But, in the process which Rajashekhar is describing is 1V, which means that network is never going to start. Please correct me if I am wrong.
I am confused at the operation of startup circuit which Rajashekar is describing @ 1:21:37. When the supply is slowly increasing from 0 and still hasn't reached VDD ( 1V or 1.8 ) , how can you assume the gate voltage of M9 to be pulled low? Lets say the Vt of device be 0.7 ( both PMOS and NMOS), then the supply has to be at least 4 Vt for the startup network to work. But, in the process which Rajashekhar is describing is 1V, which means that network is never going to start. Please correct me if I am wrong.
good morning sir, can you provide slides on this meeting
how to find polarity f op_amp sir
Promo>SM 🙋