Please clarify my doubt Sir, correct me if i am wrong . Sir i think you gave wrong connection for CLK in up counting and down counting because in last video you gave table if it is negative triggering for up counter Q should connect as CLK to next flip and and for down counter Q(bar) should connect as CLK to next flip flop For postive triggering up counter Q(bar) should connected as CLK and down counter Q should be connected as CLK to next flip flop Here in this video you used postive triggering and gave according negative triggering connections
The counter covered on the previous video was asynchronous counter. This is synchronous counter. The condition which you have mentioned are valid only for asynchronous counter.
I have already shown the design procedure in the second part of the video for designing a synchronous counter of arbitrary sequence. You may refer that.
In 3:38 when u were showing Excitation table of JK Fip Flop, the outtput Qn and Qn+1 is in the wrong sequence. Qn must be 0,0,2,1 ehie Qn+1 must be 0,1,0,1.??
I think you didn't understand the meaning of the excitation table. Please check the earlier video of JK flip-flop, where I have explained the excitation table of JK flip-flop. Here is the link: ruclips.net/video/LOPHyHOMcLI/видео.htmlsi=dCZu1bckU6SCCSIo&t=739
It is synchronous circuit. What you are saying would be true for the asynchronous counter. Here, all flip-flops are responding to the input at the rising or falling edge. So, at given clock edge, whatever is the input of the flip-flop, accordingly they will generate the new output. And the next flip-flop will respond to this new output at the next clock edge. I hope, it will clear your doubt.
I think since you have been asked to design the counter only using JK flip-flops and NOR gates, it would be easier to design an asynchronous MOD-7 counter. (unless you have been asked specifically to design synchronous counter). In that case, you need to connect the Q2, Q1, and Q0 output of the JK flip-flops to NOR gate. And the output of the NOR gate to clear input of the flip-flops. When the count goes to 111, then output of the NOR gate will become 0, and it will reset all the flip-flops. The counter will count from 000 to 110. This video will be more suitable for you. ruclips.net/video/OvOXRQiRzas/видео.html Please check it. Your doubts will get clear for sure. And still if you have any doubt then let me know here.
This is synchronous counter. So, all the flipflops in the counter receives the clock at the same time. In asynchronous counter, the output of one flip flop is connected to the clock input of next stage. I hope, it will clear your doubt.
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Best video on synchronous counter👌🏻👌🏻
FANTASTIC AS USUAL
good work
Fantastic presentation
exactly, atfer aeeing this I want to say fantastic
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The best 🗣️
Please clarify my doubt Sir, correct me if i am wrong .
Sir i think you gave wrong connection for CLK in up counting and down counting because in last video you gave table if it is negative triggering for up counter Q should connect as CLK to next flip and and for down counter Q(bar) should connect as CLK to next flip flop
For postive triggering up counter Q(bar) should connected as CLK and down counter Q should be connected as CLK to next flip flop
Here in this video you used postive triggering and gave according negative triggering connections
The counter covered on the previous video was asynchronous counter. This is synchronous counter. The condition which you have mentioned are valid only for asynchronous counter.
Please what textbook would you recommend for practice questions on digital electronics
Digital Electronics by m. morris mano and second one is digital electronics by anand kumar
@@ALLABOUTELECTRONICS thank you
@@ALLABOUTELECTRONICS sir u have solution manual of fundemental of digial by floyed editiion 11??
Sir, can we know which video editor or software you are using to make videos?
Can u help me i net to make synchrine counter from 9-0 only odd numbers for tomorow 13.6.2024
I have already shown the design procedure in the second part of the video for designing a synchronous counter of arbitrary sequence. You may refer that.
In 3:38 when u were showing Excitation table of JK Fip Flop, the outtput Qn and Qn+1 is in the wrong sequence. Qn must be 0,0,2,1 ehie Qn+1 must be 0,1,0,1.??
I think you didn't understand the meaning of the excitation table. Please check the earlier video of JK flip-flop, where I have explained the excitation table of JK flip-flop. Here is the link: ruclips.net/video/LOPHyHOMcLI/видео.htmlsi=dCZu1bckU6SCCSIo&t=739
Sir, I think the way you calculated propagation delay is wrong.please check.because first AND gate and other ff s depends on first two ff
It is synchronous circuit. What you are saying would be true for the asynchronous counter. Here, all flip-flops are responding to the input at the rising or falling edge. So, at given clock edge, whatever is the input of the flip-flop, accordingly they will generate the new output. And the next flip-flop will respond to this new output at the next clock edge. I hope, it will clear your doubt.
How will the diagram look if we are to use NOR gate pls
I think since you have been asked to design the counter only using JK flip-flops and NOR gates, it would be easier to design an asynchronous MOD-7 counter. (unless you have been asked specifically to design synchronous counter).
In that case, you need to connect the Q2, Q1, and Q0 output of the JK flip-flops to NOR gate. And the output of the NOR gate to clear input of the flip-flops. When the count goes to 111, then output of the NOR gate will become 0, and it will reset all the flip-flops.
The counter will count from 000 to 110.
This video will be more suitable for you.
ruclips.net/video/OvOXRQiRzas/видео.html
Please check it. Your doubts will get clear for sure.
And still if you have any doubt then let me know here.
❤❤
sir in 12:12 shouldnt the F/F be negative edge triggered since the Q1 transitions taking place at falling edges(1-0) of Q0?
This is synchronous counter. So, all the flipflops in the counter receives the clock at the same time. In asynchronous counter, the output of one flip flop is connected to the clock input of next stage. I hope, it will clear your doubt.
@@ALLABOUTELECTRONICS ty sir got it :)