I just clapped with joy at the end. 👏👏 You cannot imagine how fast I understood everything after watching this video...I just enlightened my class knowledge 100 times! The best Electronic course tutorials are here my fellow engineers.
Wow! With this knowledge, the possibilities are endless. Imagine, instead of clearing each flip flop's state to zero, you use the same NAND gate but connect it to PST and CLR on each FF in a different way. You could manipulate this to use counters to skip to different values
Sir, you should also mention that we are observing Q as the output...(in the neg-pos edge triggered section in the beginning of the video). And thank you very much for such great videos..appreciate your effort!
Can't appreciate your amazing explanation enough! Just a simple correction- I think (at 7:55) the signs of the NOT gates should be mirrored, for Qc and Qa. Correct me if m wrong here...!
Hello, if I have a asynchronous/ripple D flip-flop counter with a count sequence of 10, 9, 8, 7, 6, 5, 4, 3 and repeat but with provition for a logic 0 output on 8 and a logic output on 6, how exactly would I go about with this kind of a question. I understand that I will use the positive egde triggered and Q would be the clock. I would the connect the NAND gate with input 3 to clear to ensure that it will repeat the sequence but what of the provitions and would the sequence start at 15 and go down or would I also need to connect a NAND gate to PRE so it starts at 10. Any help would be much appreciated.
When to take output in counter with respect to clock pulse in negative edge triggered flip flop?? 1)At the start of clock pulse or 2)At the end of clock pulse
the outputs have to be 1010 for not gate to reset the contour so since the outputs are 1010 does that not mean we are already showing number 10 on the display before resting??? please help Im really confused about this. Thank you all.
So for ripple counters, all we need to do is determine the number of states we have in the count sequence and then attach the clocks according to the type of edge trigger? Do we use synchronous counters to implement the circuitry for sequences that skip states like 0, 1, 2, 4, 6?
sir, if we use +ve edge triggered clock then what about race around condition ?? you taught that to overcome race around condition we use -ve edge triggering .
You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs.
Thank you so much sir. Your videos have be very helpful in my studies. It's just that we cannot find any serial order in your videos which makes it difficult to find which video is next. If you could add a serial order in your videos it would be very helpful.Thank you.
Good morning sir. You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs. Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately? Am I missing something? Thank you for the lectures.
sir pls i have doubt about it,,is it ic 7490 ripple counter,,because when I reffer ic 7490 ripple counter internal diagram it's seems like little different from u mentioned in video pls suggest fast i have exams 2 days after
sir in case we have 1100 as input to nand gate ... Qd=1 and Qb=0. by taking there nand gate we have output equal to 1 so our clr input goes to state 1 thus our counter is not goingto be reset in this case..... plz clear this confusion as soon as possible bcz i have exam in next week
sir if I make a flip flop then how would I know that it is a positive edge triggered or negative edge triggered flip flop or level triggered. I know that what is positive /negative / level triggered but how do I implement this triggering?
in 2:09 when you are discussing positive edge trigger you are telling about the clock but not about the output clear from where you are taking the output when positive edge triggring
he give 2 clock inputs a and b ,,output of 1st flip flop not given to second as clock,,he gives 2nd input to second flip flop and then ckt is similar,,an logic used that is also different
It's not that we can just pass our semester exams with ur lectures ..... it's all GATE level content that u r teaching for free👏👏👏 Hat's off to u sir
I just clapped with joy at the end. 👏👏 You cannot imagine how fast I understood everything after watching this video...I just enlightened my class knowledge 100 times! The best Electronic course tutorials are here my fellow engineers.
Thank you so much for all the DE videos...they helped me score really good in my finals...
i learnd more stuff in a 9min video than a 90min lecture
rather 4.5 min at 2x speed
I feel you..
same man this is excuse i gave to my family when they ask why you arent going university
@@owaiswasim8911 🤣
I wish this guy could cover all of my undergrad degree because his videos are much better than 90 min lectures
sir its only because of ur videos i cleared my exam..thnx a lot..keep it up
hopefully +1
Your lectures are really amazing sir ! I used to hate this subject before I watched ur videos ! Atleast now I am comfortable with it !
I wish I found your videos sooner. This helped me so much thank you so much for making these videos
U JUST SAVED MY LIFE THIS SEMESTER
Heroes fight for their people from behind their masks.
Neso Academy fights for students from behind an electronic board.
not a suitable dialogue
good try 🤣
😁 benki🔥
Thank You So much Sir...it's just because of you i am able to understand Digital Logic circuits course which is in my present semester.
Thank you sir, you have exceptional teaching skills!
Wow! With this knowledge, the possibilities are endless. Imagine, instead of clearing each flip flop's state to zero, you use the same NAND gate but connect it to PST and CLR on each FF in a different way. You could manipulate this to use counters to skip to different values
Your videos are really great. Thank you so much. I cleared my exams with good grade.
sir ur lectures are truly worth it gave me great understanding .
sir i also want a lecture on how to design a counter which have only the even states.
all your lectures are superb sir.
thanks a lot!!
tommorow is my dld exam.hoping to get good marks because of your videos.
the lectures are very interesting, THANKYOU very much for the videos
Sir, you should also mention that we are observing Q as the output...(in the neg-pos edge triggered section in the beginning of the video).
And thank you very much for such great videos..appreciate your effort!
i don't have any words to thank u
Thank You Very Much! Your videos have helped me alot.
All the lecturers r awesome...I had cleared all my doubts.... specially I liked the flip flops lectures the most.... thanks a lot to neso academy
thank you so much sir these videos are so much helpful
man you are awsummm.. thanx alott fr videos.. bhot duaa milega humlog ka.. God bless
Thank you so much sir
Your videos helps me alot
Thanks Neso i learnt better than 1 hr lecture in college #from #Nepal
Thanks sir .Watching from Nepal
In my book it says to draw kmap for output states then draw circuit for clear input. Here we are taking just the first invalid state
its my exam today and at 3:00 am I am listening to your lecture ......... thnks sir
And me at 5:00 am
M1 at 237
I was struggling for 3 hours with a problem. Thank God I watched this video!
One minute into the video and ta-da ! Problem solved. :)
Now I'm confident about my interns. Thank you
bache ki jaan bachali apne bauji ,dhanyawad :))
This is very helpful.Thank you sir
thanks this qs came in exam but with a twist qs was
design a ripple decade counter using jk ff without clr and preset signals
for positive edge triggered FF the race around condition will appear.How could it be used as counter?could you please explain.
Can't appreciate your amazing explanation enough!
Just a simple correction- I think (at 7:55) the signs of the NOT gates should be mirrored, for Qc and Qa. Correct me if m wrong here...!
Yup that's correct!
@@shubhranginidas6818 ohh wow u r clearing his doubt after 1 year
Pakka explanation..... awesome.thank you sir
thank you.........this helped me a lot really!!😉😃
Thanks for your help
great jop sir that's amazing
Thank you for the important notes in the beginning of the video. That's what the lecturer did not explain which confused everyone LOL
you are a gift from the god to us
thanks, now i am understanding the working of computer
number 1 content.
Tqs bro u helped me my exam will start 10:00 clock
thanks alot man respect
Hello, if I have a asynchronous/ripple D flip-flop counter with a count sequence of 10, 9, 8, 7, 6, 5, 4, 3 and repeat but with provition for a logic 0 output on 8 and a logic output on 6, how exactly would I go about with this kind of a question. I understand that I will use the positive egde triggered and Q would be the clock. I would the connect the NAND gate with input 3 to clear to ensure that it will repeat the sequence but what of the provitions and would the sequence start at 15 and go down or would I also need to connect a NAND gate to PRE so it starts at 10. Any help would be much appreciated.
you are great master
The besttt teacher ever
MAN YOU ROCK!!!!!
Thank you for best teachings...
1 question : why not to use and gate instead of nand gate?
Hi ..how is the clear input have inverter (bubble form) if the zero out of NAND gate its will be logic 1 ?
U r great sir....
Excellent.
if we place positive edge trigger how can it be JK flipflop??
When to take output in counter with respect to clock pulse in negative edge triggered flip flop??
1)At the start of clock pulse or
2)At the end of clock pulse
Can you explain any explain in which clear is applied to particular filp flop.. Eg if 4ff are there and in only 2ff clear is used.
you drew the NOT gate symbol in the wrong direction
Could you please explain how can I make 4 bit up/down BCD ripple counter?
the outputs have to be 1010 for not gate to reset the contour so since the outputs are 1010 does that not mean we are already showing number 10 on the display before resting???
please help Im really confused about this. Thank you all.
sir u r the best
good explination man..
Excellent logic bhayyaa
These videos are really appreciating but in BCD counter we have to use truth table and k - maps while making the mod 10 counters.
when to use nand gate/ and gate for clr input
u have giiven bubble at clr means if u remove bubble then u may use and?
Very nice :)
At time 7:11Not gate symbol is reversed and also 7:21 is also reversed. Explanation is very good.
A small Mistake is that when using CLEAR (Qd,Qc,Qb,Qa)=0 then when you are using NAND gate inputs should not be Qd and Qb instead Qd NOT And Qb NOt.
Ty sir for videos !!! This saved my life .
Could you please tell me how to build a 2 digit counter which can be used to count upto 10
Excellent 👍
So for ripple counters, all we need to do is determine the number of states we have in the count sequence and then attach the clocks according to the type of edge trigger? Do we use synchronous counters to implement the circuitry for sequences that skip states like 0, 1, 2, 4, 6?
Yes we use synchronous counters to implement the circuitry for sequence that skips states
earlier in down counter video, you used negative edge triggered and Q as clock, you have not mentioned that in this lecture?
it is very easy method for all ece students
sir, if we use +ve edge triggered clock then what about race around condition ??
you taught that to overcome race around condition we use -ve edge triggering .
+sumit shekhar LPC
It takes place in level triggering
To overcome it we use 3 methods
1)(T/2)>FF propagation delay
2) edge triggering and
3) master slave JK flip flop
Nice explanation
Please release video about timing diagram & truth table for 3 bit synchronous counter
You have explained that we have to clear the counter after 1001 (9).
So upon the arrival of 1010 we clear the counter.
My question is when
Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since
Qd Qc Qb Qa are our outputs.
That is exactly my question i think the number 10 would also be displayed since we have 1010 before resat???!!
how to make a counter which start from any no. that we want
for ex. i want a counter which counts from " 3, 4, ...,8".
plz explain.......
Great
you are very good sir thanks
Thank you so much sir. Your videos have be very helpful in my studies. It's just that we cannot find any serial order in your videos which makes it difficult to find which video is next. If you could add a serial order in your videos it would be very helpful.Thank you.
Can anyone tell me the difference between designing a BCD counter using jk ff and BCD ripple counter using jk ...are they same?
sir u r awessome ..
How to do for 11 decimal equivalent no. Is this 11 resets to zero or 1.
Good morning sir.
You have explained that we have to clear the counter after 1001 (9).
So upon the arrival of 1010 we clear the counter.
My question is when
Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since
Qd Qc Qb Qa are our outputs.
Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately?
Am I missing something?
Thank you for the lectures.
same question
They are asynchronous so output will not wait for next trigger and went off
What is the equations for j, k input? Because if i apply k-map the answers are different then =1
What do you mean by (MN) wheather M*N or simply MN at the time of cascading the counters??
sir pls i have doubt about it,,is it ic 7490 ripple counter,,because when I reffer ic 7490 ripple counter internal diagram it's seems like little different from u mentioned in video pls suggest fast i have exams 2 days after
thank you neso
sir in case we have 1100 as input to nand gate ... Qd=1 and Qb=0. by taking there nand gate we have output equal to 1 so our clr input goes to state 1 thus our counter is not goingto be reset in this case..... plz clear this confusion as soon as possible bcz i have exam in next week
sir if I make a flip flop then how would I know that it is a positive edge triggered or negative edge triggered flip flop or level triggered. I know that what is positive /negative / level triggered but how do I implement this triggering?
How about if I want to count from 9 to 0, using 7476 F-F's?
thank you
the best
How about if i use a 3 input nand gate how will it work to reset to zero
awesome
Sir for MOD-12 asynchronous down counter.. We can it solve same as solved for MOD -6
Ty✌
in 2:09 when you are discussing positive edge trigger you are telling about the clock but not about the output clear from where you are taking the output when positive edge triggring
he give 2 clock inputs a and b ,,output of 1st flip flop not given to second as clock,,he gives 2nd input to second flip flop and then ckt is similar,,an logic used that is also different