my semesters are near and this subject is difficult for me ....but now i must say this subject was very difficult for me ..... cause you have cleared all my doubts thanks a lot ma'am ... loved the way you taught ...so simple it is now for me ....❤❤😊😊😊
Thank you for posting so many well spoken and easy to understand videos on pipelining, forwarding and similar subjects! My professor wishes she could teach as well as you :) Hope all is well
Thank you so much for the appreciation... means a lot... yes... all's good.. m a bit busy in sm things, so have not been able to post new videos lately... will be resuming shortly.. :)
@@ritukapurclasses1591 May almighty shower his unconutable blessings upon you &your family &May you live long.. Ma'am can you suggest me what should I study from architecture for net May 2021.. I am very much confused about what to study & what not..
Thankyou so much for you lectures mam. These are really helpful and understandable for my semester exams. Mam please upload a video on control flow instructions. Will be very helpful.
Please refer to the first video in the same playlist: Pipelining Concept and Numericals (ruclips.net/video/6DjU1ZCM-Ko/видео.html). You can directy move to 3.04 seconds if you are short of time. We are basically computing 1 Clock Cycle Time in a Pipelining System (Used to find the speedup in the following videos)= max (Time taken in respective stages) + Register Delay (if any). The standard derivation discussed can be also verified from some good Computer Architecture books (you may read page page 267 of chapter 6.1 in Advanced Computer Architecture of Kai Hwang (2001 edition)).
You are given two simple processors-one using a single-cycle design, the other a basic 5-stage pipeline-in which the instruction stages take the following amount of time: • Fetch (IF): 20 ns • Decode (ID): 25 ns ,• Execute (EX): 30 ns, • Memory access (MEM): 40 ns, • Write back (WB): 25 ns How much time does each processor take to execute a single instruction? How can i solve by easy method ?
In which cases Execute stage takes more than 1 clock cycle? Is it true that if there is any floating point operation involved then it will take more than one clock cycle? Please explain, in which cases IF and WB take more than one clock cycle.
may be you are getting correct answer but your solution is wrong please update that. i1, i2, i3 nd i4 are instruction not tasks . tasks will be inside table and instructions will be at left end side . answer is fortunately correct but solution is not correct
It is mentioned dat these r instructions nd not tasks. Also there may me multiple ways to solv a question. So you cannot say a particular method to be wrong or right. Further you can verify this method for solving multiple questions and ull get correct answer fr each.
Great..
you made me to understand this non uniform stage delay pipelining concept... Thanks
my semesters are near and this subject is difficult for me ....but now i must say this subject was very difficult for me ..... cause you have cleared all my doubts thanks a lot ma'am ... loved the way you taught ...so simple it is now for me ....❤❤😊😊😊
Thank you... Means a lot...
mam I want to take tuitions from you. your way of explaining is very appreciable. All things all clear thank you so much
let me know the subjects you are interested, and we will see if we can start a batch :)
Thank you for posting so many well spoken and easy to understand videos on pipelining, forwarding and similar subjects! My professor wishes she could teach as well as you :) Hope all is well
Thank you so much for the appreciation... means a lot... yes... all's good.. m a bit busy in sm things, so have not been able to post new videos lately... will be resuming shortly.. :)
thankyou for your explanation
Thanks aunty for this video
Aunty hogi teri mumy🤬🤬
Tysm for your explanations..it helped me a lot..
Will u please make a video on cache memory..it will be really helpful then
Ma'am I like your architecture videos... Great interest in watching..
100%understandable...
Allah tala aapko kamyaabi dai hamesha
Thank you so much for the appreciation and wishes... Means a lot...
@@ritukapurclasses1591 May almighty shower his unconutable blessings upon you &your family &May you live long..
Ma'am can you suggest me what should I study from architecture for net May 2021..
I am very much confused about what to study & what not..
Thank you mam for make this video 🥺🥺 .You have explained very nice 😇😇
Thank you 😊
Finally i solve my problem..thanks mam its really helpful video...
Thank you...
not sure whether your voice is beautiful or the explanation is good but i liked the video
Not sure if you wanted to learn or lurk, but I found your comment disgraceful and lacking respect.
you were a real help
....thanks alot
Thank you...
Your voice is nice...
Thanks a lot mam! It really cleared my doubts.
Thank you :) Means a lot...
Ma'am total time will b:4+4-1*tp=91 ns
Thank you very much. It really helped me.
Thank You dear
way of teaching is very nice
Why there is no operand fetch in table
hi mam your explanation is too good.i have one doubt in this video.how to calculate tp.that is how to get ans13(n+k-1)
Thank you 😊A step-wisw solution to your query is shown here: ruclips.net/video/39jTWT4cIzs/видео.html please let me know if it is clear from here
Thankyou so much for you lectures mam. These are really helpful and understandable for my semester exams. Mam please upload a video on control flow instructions. Will be very helpful.
Thank you. Means a lot! Sure, I'll try to upload it very soon..
Worth it lecture to watch, Excellent
Way of teaching Nd voice modulation is very imp for teaching, u r Osm ...only once fasaak,🤪
Mam,
Why are we taking the max of a particular stage.
Please refer to the first video in the same playlist: Pipelining Concept and Numericals (ruclips.net/video/6DjU1ZCM-Ko/видео.html). You can directy move to 3.04 seconds if you are short of time. We are basically computing 1 Clock Cycle Time in a Pipelining System (Used to find the speedup in the following videos)= max (Time taken in respective stages) + Register Delay (if any). The standard derivation discussed can be also verified from some good Computer Architecture books (you may read page page 267 of chapter 6.1 in Advanced Computer Architecture of Kai Hwang (2001 edition)).
good
Thank you 🙂
i hope you are getting my point
❤
You are given two simple processors-one using a single-cycle design, the other a
basic 5-stage pipeline-in which the instruction stages take the following amount of
time: • Fetch (IF): 20 ns • Decode (ID): 25 ns ,• Execute (EX): 30 ns, • Memory
access (MEM): 40 ns, • Write back (WB): 25 ns
How much time does each processor take to execute a single instruction?
How can i solve by easy method ?
keeping camera still would have been superb...
though nc vdo
Supper scaler pipllining
Thank you 😊
@@ritukapurclasses1591 Ma'am kindly make a video on Supper scalar piplining.☺❤
Sure...
@@ritukapurclasses1591 Thanks in anticipation
although i would like it very much if you also upload a video of 8086 architecture
Sure.. I'll try to do it very soon..
May u explain the topic- reservation table of general pipelines
simply AWESOME...
Thnkyou...
love it
so simple
very helpful thanks
Glad it helped
Simply awesome 👍
In which cases Execute stage takes more than 1 clock cycle? Is it true that if there is any floating point operation involved then it will take more than one clock cycle?
Please explain, in which cases IF and WB take more than one clock cycle.
may be you are getting correct answer but your solution is wrong please update that. i1, i2, i3 nd i4 are instruction not tasks . tasks will be inside table and instructions will be at left end side . answer is fortunately correct but solution is not correct
It is mentioned dat these r instructions nd not tasks. Also there may me multiple ways to solv a question. So you cannot say a particular method to be wrong or right. Further you can verify this method for solving multiple questions and ull get correct answer fr each.
I wna pass my csa exam 2moro can u give me a list of some imp concepts 😅
How was it ?
👍👍
Can you please upload a video on AMDHAL'S law.?
Sure.. I'll do so very soon...
i dont think the chart is filled correctly .this is incorrect way of filling the chart
Great
Thank you 😊
Thanks mam😊
This is 4 segment instruction pipeline?
☺❤
😊 Thank you for your appreciation...
excellent
Thank you! Cheers! :)
For 5 segment
No operand fatch in table but it comes first before execution
for I1, it takes 6ns and 7ns for I2. Am I wrong?
you have stolen my pen😜😁
RIP english writing