Negative edge-triggered JK Flip Flop with CLR' and PRE' input.

Поделиться
HTML-код
  • Опубликовано: 14 июн 2021
  • Please subscribe my channel using gmail or hotmail or any other email id, don't subscribe it using your university/college email id. because it will not count.
    This video explains the working of Negative edge-triggered JK Flip Flop with CLR' and PRE' input. The priority of the CLR', PRE', and CLK is explained.
    Draw the output waveform of Q for a negative edge-triggered JK flip flop with active LOW CLR' and PRE' by using the input waveform.
    How the positive edge-triggered D Flip Flop works with PRE' and CLR' Inputs.
    • D Flip Flop working wi...
    Working Of Active High SR Latch (SR Latch using NOR Gate) for S and R Input waveform.
    • Working Of Active High...
    Mantissa and exponent of 5 representing in Binary floating point.
    • 5 Represented In Binar...
  • НаукаНаука

Комментарии • 7

  • @Harb.991
    @Harb.991 Год назад +1

    YOU ARE THE BEST GIRL!!
    Thank you so much, that was very clear!

  • @kulwashija1616
    @kulwashija1616 2 года назад +1

    Good lecture 👊👊👊

  • @amangupta5164
    @amangupta5164 7 месяцев назад +1

    Ma'am we know when the value of clock is zero then the output come out to be previous value
    But yaha apne jab 1st time clock ko consider kiya tab apne output 1 diya 0 nahi hona chahiye tha wahan?

    • @digitekkeys2024
      @digitekkeys2024  7 месяцев назад +1

      Since it was not specified that initially all the outputs are zero so I have considered the waveform conditions. Pre' waveform is initially zero so output can be one. Also, during output waveform drawing you can specify that you are considering initially all the outputs are zero then you can take it zero.