Linear delay model | Delay in Multistage Logic Networks | Logical Effort

[@skjohn7502]

Sir THANK YOU SO MUCH ........ After a long search i found your video for VLSI where I can able understand easily its very useful sir...but why sir u didnt upload other topics ,?

[@Fpg-x2s]

Sir
Thanking you very much.
Good to learn deeply.
Once again I thank your kindself.
Best Regards
Gopal Raju

[@pmanasa4383]

Tqsm for such a good explanation sir.
Much ❤ from Karnataka

[@arzcellent]

Thank u

[@jesman2186]

Sir neegala.... voice semma😍

[@arzcellent]

Yes.

[@tsivachidambarampillai1131]

good explaination,can you tell the name of the book referred sir.

[@tnpscbooks]

Super sir 🎉 sir please upload vlsi design stick diagram & lambda based design rule sir

[@tamildesiyathalaivarprabakaran]

nandri

[@harshabhrito]

Sir elmore delay model um ethum same aa

[@AnniLalin]

👍

[@karthikeyakumar2961]

n=4
g=20/3
h=2
p=6
f=40/3
d=58/3
tell me is this correct ?

[@arzcellent]

yes

[@lofi_song562]

How g=20/3 can u explain

[@lofi_song562]

It should be 20/9

[@karthikeyakumar1275]

Sorry bro I don't remember I have done that course

[@piyushpuri1977]

Sir hindi m hi bol lete h
Language barrier ...?

[@arzcellent]

Thanks. We will add captions.