The many moments in wich a real inside-working on the component nivo was explained made this second part of three an extra worthly source of that so looked-for knowledge. That's the sort of usefull understanding-giving insights that makes these videolessons so needed for many of us
Thank you Professor. This title reminds me of thermal fatiguing in power semiconductors. I read something - maybe 30 years ago - I think in RCA data. It stated that the then highest reliability, military power transistors would withstand 30,000 full temperature cycles before the chip detached from its header - obviously resulting in failure. 30,000 may not be such a big number in this connection. This might be an interesting - even vital - topic.
@13:44 isn't the reverse recovery time of the MOSFET body diode is high as it is slow diode but you have mentioned its fairly low...Could you please clarify it?
Thaanks for comment. Yes it is a slip of the togue. trr is longer for MOSFET body diode. The end of that sentence that Qrr is larger is of course correct.
@2:52 dear sir in the general app notes I have observed that switching loss due to rise and fall time equation there is factor 1/2 but in your video it is 1/3 ...I am not able to correlate both ....where I am getting wrong?
Hi, Thank you for the comment. None of of derivation is in fact correct since parasitics will affect the losses. The difference between the expressions is the way the problem is posed. In the video I am not taking into account the reverse recovery of the diode while in other publications they include it. The main point I was making that the losses are linear with frequency. The best way to estimate switching losses is by simulation .
Hello Sam, a quick question on power losses in transistor in LLC topology. There is R-ds-ON (static) loss, no turn ON loss as ZVS, there is turn-OFF loss due to magnetising current. Q: losses due to Coss/Eoss, are these losses ZERO in LLC design?
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The many moments in wich a real inside-working on the component nivo was explained made this second part of three an extra worthly source of that so looked-for knowledge. That's the sort of usefull understanding-giving insights that makes these videolessons so needed for many of us
Thank you again Rob for the insight.
Thank you Professor.
This title reminds me of thermal fatiguing in power semiconductors. I read something - maybe 30 years ago - I think in RCA data.
It stated that the then highest reliability, military power transistors would withstand 30,000 full temperature cycles before the chip detached from its header - obviously resulting in failure. 30,000 may not be such a big number in this connection. This might be an interesting - even vital - topic.
Thanks for note and sharing. Good suggestion. Will consider
@13:44 isn't the reverse recovery time of the MOSFET body diode is high as it is slow diode but you have mentioned its fairly low...Could you please clarify it?
Thaanks for comment. Yes it is a slip of the togue. trr is longer for MOSFET body diode. The end of that sentence that Qrr is larger is of course correct.
excellent . . . on to part 3
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@2:52 dear sir in the general app notes I have observed that switching loss due to rise and fall time equation there is factor 1/2 but in your video it is 1/3 ...I am not able to correlate both ....where I am getting wrong?
Hi, Thank you for the comment. None of of derivation is in fact correct since parasitics will affect the losses. The difference between the expressions is the way the problem is posed. In the video I am not taking into account the reverse recovery of the diode while in other publications they include it. The main point I was making that the losses are linear with frequency. The best way to estimate switching losses is by simulation .
Sir, Do you have switching loss example
This is rather difficulty as there are so many possible cases. The best is to do simulation onyour application.
Hello Sam, a quick question on power losses in transistor in LLC topology. There is R-ds-ON (static) loss, no turn ON loss as ZVS, there is turn-OFF loss due to magnetising current. Q: losses due to Coss/Eoss, are these losses ZERO in LLC design?
There is still turn off losses due to some overlap but no Cds losses thanks to the self commutating
Thanks
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🙏🙏❤️🙏🙏
Thanks