3:00 Please correct me if I am wrong but if the flip flops are negative edge triggered, data changes in the flip flop only for the NEGATIVE EDGE of the clock not on both edges (in the timing diagram)?
In the first part of the video, why the inputs were drawn, on the time diagram, up to only the second clock? Shouldn't they be up to the fourth clock for serial format and up to the first clock for the parallel format?
yeah i was wondering about the same thing. But i think that since he didn't mention anything about the type of the clock, the timing diagram is not correct nor wrong. But if u were assuming that the FF is negative edge triggered, the timing diagram in the serial form should be up to the fourth pulse, while in the parallel form each input up to the 1st pulse.
@@evanaw1164 @Omar Ahmed i may be wrong but i think the reason behind why serial inputs were drawn up to the second clock is because of using (master and slave f/f.). by using master and slave f/f we can get the output in (half clock cycle). ITs done to use the clock cycles more efficiently and not wasting it. (correct me , if i m wrong). AS far as why parallel inputs were drawn upto fourth clok cycle, for this yes, we are on the same page. I also think that those line (for parallel inputs), should be drawn up to one half clk cycle.
Sir, what is the difference between serial and parallel types,in terms of their usage? Why we call serial type as temporal code and parallel type as spatial code?
Because all four flip flops synchronized with same clock. In simple words, A flip flop changes state once in clk pulse cycle and everyone provided with clock pulse train having same time period!!
shouldn't the input of D be 1, 1, 0, 1 for the serial form? if the input was 1(1st tick), 0, 1, 1, the data interpreted in the flip flops would actually be in the inverse direction (1101) or in other words first in first out. the clock of the flip flop should also be determined, whether it is positive or negative edge triggered(and the timing diagram of the serial input D should adjust accordingly) which means, the D will change only after 1 full period of each pulse, not half of it.
Bro I got highest in my class in Digital Electronics after watching your videos :)
Very good bro, Congratulations...
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I also got A+ in my semester exam.
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You are lord of teaching
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Yes bro, excellent teaching....
Neso academy is doing a great job. Thank you so much.
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really i maintaining notes of your lectures sir and im using this concepts in rtl coding sir..
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Thanks a lot for such an informative video
Yes, really super class....
3:00 Please correct me if I am wrong but if the flip flops are negative edge triggered, data changes in the flip flop only for the NEGATIVE EDGE of the clock not on both edges (in the timing diagram)?
your teaching skills excellent
Yes bro, really good class....
Abhi na muze apk mili aestrotech nam ki 🥰
Good thanks learnd ALOT
perfect lectures
Yes, really super class....
very good lectures
Another great video from Neso Academy.
Nice explanation sir,tq
Pls recheck at 2:00 on right side statements for serial and parallel inputs are written opp.
Very helpful!
Yes bro, really super class....
Watching after 8 years ❤
thanks a lot. It was best.
In the first part of the video, why the inputs were drawn, on the time diagram, up to only the second clock? Shouldn't they be up to the fourth clock for serial format and up to the first clock for the parallel format?
yeah i was wondering about the same thing. But i think that since he didn't mention anything about the type of the clock, the timing diagram is not correct nor wrong. But if u were assuming that the FF is negative edge triggered, the timing diagram in the serial form should be up to the fourth pulse, while in the parallel form each input up to the 1st pulse.
@@evanaw1164 @Omar Ahmed i may be wrong but i think the reason behind why serial inputs were drawn up to the second clock is because of using (master and slave f/f.). by using master and slave f/f we can get the output in (half clock cycle). ITs done to use the clock cycles more efficiently and not wasting it. (correct me , if i m wrong).
AS far as why parallel inputs were drawn upto fourth clok cycle, for this yes, we are on the same page. I also think that those line (for parallel inputs), should be drawn up to one half clk cycle.
Thank you) you've helped me a great deal.
Thank you💯❤
face reveal?
Hey can u plz make video lectures on brief introduction on verilog & verilog for combinational circuits..
you are my savior
Great
Sir why has data in parallel input continued to be high for two clock cycles ?
should be drawn up to one half clk cycle
Sir, what is the difference between serial and parallel types,in terms of their usage?
Why we call serial type as temporal code and parallel type as spatial code?
good explaination
Yes, really super explanation....
sir 1011 is stored at every positive edge or negative edge of the clock, but u made at every change in clock which is like the latch
opertaion
yes i have the same doubt
Good teaching...
Yes, really super class....
Thanks teacher
Thank you🙏
it is temporal code and spatial code (not special code)
nice lol
thanks
Hmm
@@careerladderupsc at least he contributed something, wbu? lol
To know more than everything!
@@careerladderupsc
I am still in confusion ...Why only one clock pulse is used on PIPO?
यह कहके तूने अपनी मां बहन को गाली दी है
In jam single clock cycle, the input must reach the output....
As the filp flop are negative edge triggered , in serial form it will remain one for the first negative edge.
6yrs old but still gold
Temporal code and spatial code? temporal is time related and spatial is space related. Am I wrong?
Please engneering electromagnetics upload please
That is difficult
Ya Bro pls
thanks a lot
Try linking the next vide on the descriptions
Thank you i love you
Yes, really super class....
In anand kumar it is given that parallel in,parallel out is Shift Register?
Yes, it is a shift register...
thank you
sir, as q3 is connected to d2 so, when we get q3 as 1 (in first cycle) d2 should also be 1
why d3,d2,d1 ,d0 are taking same time as in parallel mode?
Because all four flip flops synchronized with same clock. In simple words, A flip flop changes state once in clk pulse cycle and everyone provided with clock pulse train having same time period!!
Adding Bubble at the clock indicates -ve and arrow indicates the edge triggering so o> adding to clock means it is -ve edge triggering flop flop
sir plz make videos on DAC and ADC converter plzz
Hi, you can find converter videos ADC and DAC in my channel....
Is SISO and shift register the same thing?
Yes, SISO is a type of shift register, SISO means Serial In Serial Out....
I could not find the A to D and D to A, please help me
In my channel ADC and DAC is available....
Siso, pipo ics are available in market
Yes, ICs are available in the market
Thanks
sir please give the pdf notes about "Digital Circuits"
please upload a/d d/a converters and op amp
Hi, you can find ADC and DAC videos in my channel....
damn i was waiting for him to call hi peepo but well..i guess PIPO is fine
You mean Parallel In Parallel Out...
pls upload some vides on memory orsend me a link
shouldn't the input of D be 1, 1, 0, 1 for the serial form? if the input was 1(1st tick), 0, 1, 1, the data interpreted in the flip flops would actually be in the inverse direction (1101) or in other words first in first out. the clock of the flip flop should also be determined, whether it is positive or negative edge triggered(and the timing diagram of the serial input D should adjust accordingly) which means, the D will change only after 1 full period of each pulse, not half of it.
Is SIPO is storage register too??
Yes it can be used for temporary storage...
@@circuitsanalytica4348 Thanks. Finally after 5 years my doubt is cleared.
special code?
"Spatial Code" not "Special Code"
siso = shift registers or not
+Neso Academy sir please provide adc and dac lecture, thankyou forr this lectures
Serial in serial out
Yes, Serial In and Serial Out
W.
Bro it's spatial
Thank you