This series might be the best explanation of the AXI protocol on youtube right now. Having someone talk me through timing diagrams is so valuable to me.
I have a question. Our memory has 0,1,2,3,4 and so on data at every address location. With the assumption that every memory location is of 1 byte, size arsize is set to 2'b01, every beat must be of size 2 bytes, so we are extracting 16bit RDATA on the 32bit RDATA line? What will the RDATA line look like? 32'h00003210 ? followed by 32'h00007654, 32'h0000ba98, 32'h0000fedc ? And now with the assumption that every memory location is 32bits or 1 word, our full burst will still have 4 beats but not on each beat rdata looks like 32'h00000000, 32'h00000001, 32'h00000002, 32'h00000003 ?
Thanks for this informative video. I have a question. Why the intervals between "0,1,2,3", "4,5,6,7", "8,9,10,11", "12,13,14,15" is different? Did it mean that the rdata will not come out without interval even though the requested data is stored in memory continuously.
Hi Dillon, Lets say the rdata and rvalid are asserted simultaneously, just like what you have show here, so what if rresp takes 1 more clk to reach back to the subordinate , will the rvalid still stretch till rresp is sampled at the subordinate's interface?
Would it be correct to say that AXI3 supports maximum bytes per read or write burst as 16 beats/burst x 8 bytes/beat = 128 bytes and while for AXI4 this would be 256 beats/burst x 8 bytes/beat = 2048 bytes ? If Read and Write happen simultaneously on same AXI port, does total bytes/burst become 2x of above calculated numbers of 0.5x of above calculated numbers ?
I haven't used AXI3, so IDK about it. Section A3.4.1 (Address Structure) of the AXI4 specification states that: "AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. Support for all other burst types in AXI4 remains at 1 to 16 transfers." The same section says that each AXI4 transfer can be up to 128 bytes, so I suppose the max bytes per transfer (if you are using INCR bursts), would be 256*128 bytes. I don't understand the second question so IDK.
@@DillonHuff Thanks for clarifying about INCR burst rate in AXI4 i.e. 256*128 =32768 bytes per burst My second question is as follows: when there is simultaneous read and write on the read and write channel of an AXI4 bus, does this burst rate of 32768 bytes per burst gets shared between the two channels ?
This series might be the best explanation of the AXI protocol on youtube right now. Having someone talk me through timing diagrams is so valuable to me.
Thanks Tim! I'm glad it was helpful.
I couldn't agree more! Thanks Huff!
Thanks a lot! I am a verification engineer working on the AXI based interconnects and your video is very clear/well presented. Really helpful!
Thanks Hui! I'm glad you liked it.
probably the only and the best video on AXI - truly a life saver.. thank you so much.. can you please do APB, CHI and other such protocols please!
It is the clearest explanation.
Thank you Dillon. Your videos are very informative. Your effort is much appreciated.
I have a question. Our memory has 0,1,2,3,4 and so on data at every address location.
With the assumption that every memory location is of 1 byte, size arsize is set to 2'b01, every beat must be of size 2 bytes, so we are extracting 16bit RDATA on the 32bit RDATA line? What will the RDATA line look like? 32'h00003210 ? followed by 32'h00007654, 32'h0000ba98, 32'h0000fedc ?
And now with the assumption that every memory location is 32bits or 1 word, our full burst will still have 4 beats but not on each beat rdata looks like 32'h00000000, 32'h00000001, 32'h00000002, 32'h00000003 ?
How is it possible to transfer 1 or more bytes in single clock? Is there only one data line or more?
The bus can be wider than one byte
@@DillonHuff does that mean bus has variable number of data lines ?
Basically the transceivers transistor is faster, then the clock. I encourage to read up on SerDes, which is the basic of all Ethernet, DDR and more :)
Thanks for this informative video. I have a question. Why the intervals between "0,1,2,3", "4,5,6,7", "8,9,10,11", "12,13,14,15" is different? Did it mean that the rdata will not come out without interval even though the requested data is stored in memory continuously.
This AXI series video are very helpful. Could you please elaborate on "beat" and "burst" ? THANK YOU!!
Is it possible to share the presentations to write comments about them?
Unfortunately no, I lost the original PowerPoints when my old laptop died. I'm sorry that I couldn't be more helpful.
Thanks, Dillon. This is very helpful.
Glad it helped Hamza
清晰易懂，Thanks a lot.
Recommend you to use wavedrom editor to make waveform diagrams. Really informative videos btw.
Yes someone else recommended that as well. I wish I had known about that tool before I started making these videos.
Thanks for watching!
Your videos are so clear to understand. I think you need to get that best graphic design awad! ;)
Thanks Sravan! I'm still waiting for it...
Hi Dillon,
Lets say the rdata and rvalid are asserted simultaneously, just like what you have show here,
so what if rresp takes 1 more clk to reach back to the subordinate , will the rvalid still stretch till rresp is sampled at the subordinate's interface?
Would it be correct to say that AXI3 supports maximum bytes per read or write burst as 16 beats/burst x 8 bytes/beat = 128 bytes and while for AXI4 this would be 256 beats/burst x 8 bytes/beat = 2048 bytes ?
If Read and Write happen simultaneously on same AXI port, does total bytes/burst become 2x of above calculated numbers of 0.5x of above calculated numbers ?
I haven't used AXI3, so IDK about it. Section A3.4.1 (Address Structure) of the AXI4 specification states that:
"AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. Support for all other burst types in AXI4 remains at 1 to 16 transfers."
The same section says that each AXI4 transfer can be up to 128 bytes, so I suppose the max bytes per transfer (if you are using INCR bursts), would be 256*128 bytes.
I don't understand the second question so IDK.
@@DillonHuff Thanks for clarifying about INCR burst rate in AXI4 i.e. 256*128 =32768 bytes per burst
My second question is as follows: when there is simultaneous read and write on the read and write channel of an AXI4 bus, does this burst rate of 32768 bytes per burst gets shared between the two channels ?
The 1st statement is correct.
For 2nd statement the the maximum bytes/burst for AXI4 is 2x of AXI3 either the read or write or for both.
thank u very much, it's very helpful
Thanks Dillon.
No problem Kartik!
Thanks a lot. It is a great job.
Thank you Rui. I'm glad you liked it!
Can you give this code?
Unfortunately there is no code for this example, I just made it up on paper. Sorry I couldn't be more helpful.
Best